[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

[Lei Huang via Phabricator via llvm-commits]

lei added inline comments.


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Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c:15
+  // CHECK-LABEL: @test_lwarx
   // CHECK: %0 = tail call i32 asm sideeffect "lwarx $0, ${1:y}", "=r,*Z,~{memory}"(i32* %a)
   return __lwarx(a);
----------------
where is the check for `CHECK-NON-PWR8-ERR:`?


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Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c:36
   // CHECK: %0 = bitcast i32* %a to i8*
   // CHECK: %1 = tail call i32 @llvm.ppc.stwcx(i8* %0, i32 %val)
   return __stwcx(a, val);
----------------
`CHECK-NON-PWR8-ERR:` check?


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Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c:2
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \
----------------
why are we only testing this for pwr9 vs pwr7/8 similar to other tests added?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D105946/new/

https://reviews.llvm.org/D105946