[PATCH] D106168: [RISCV] Compose vector subregs hierarchically
Jon Roelofs via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 16 12:33:07 PDT 2021
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG15267595fda5: [RISCV] Compose vector subregs hierarchically (authored by jroelofs).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D106168/new/
https://reviews.llvm.org/D106168
Files:
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -51,20 +51,20 @@
def ABIRegAltName : RegAltNameIndex;
-def sub_vrm1_0 : SubRegIndex<64, -1>;
-def sub_vrm1_1 : SubRegIndex<64, -1>;
-def sub_vrm1_2 : SubRegIndex<64, -1>;
-def sub_vrm1_3 : SubRegIndex<64, -1>;
-def sub_vrm1_4 : SubRegIndex<64, -1>;
-def sub_vrm1_5 : SubRegIndex<64, -1>;
-def sub_vrm1_6 : SubRegIndex<64, -1>;
-def sub_vrm1_7 : SubRegIndex<64, -1>;
-def sub_vrm2_0 : SubRegIndex<128, -1>;
-def sub_vrm2_1 : SubRegIndex<128, -1>;
-def sub_vrm2_2 : SubRegIndex<128, -1>;
-def sub_vrm2_3 : SubRegIndex<128, -1>;
-def sub_vrm4_0 : SubRegIndex<256, -1>;
-def sub_vrm4_1 : SubRegIndex<256, -1>;
+def sub_vrm4_0 : SubRegIndex<256>;
+def sub_vrm4_1 : SubRegIndex<256, 256>;
+def sub_vrm2_0 : SubRegIndex<128>;
+def sub_vrm2_1 : SubRegIndex<128, 128>;
+def sub_vrm2_2 : ComposedSubRegIndex<sub_vrm4_1, sub_vrm2_0>;
+def sub_vrm2_3 : ComposedSubRegIndex<sub_vrm4_1, sub_vrm2_1>;
+def sub_vrm1_0 : SubRegIndex<64>;
+def sub_vrm1_1 : SubRegIndex<64, 64>;
+def sub_vrm1_2 : ComposedSubRegIndex<sub_vrm2_1, sub_vrm1_0>;
+def sub_vrm1_3 : ComposedSubRegIndex<sub_vrm2_1, sub_vrm1_1>;
+def sub_vrm1_4 : ComposedSubRegIndex<sub_vrm2_2, sub_vrm1_0>;
+def sub_vrm1_5 : ComposedSubRegIndex<sub_vrm2_2, sub_vrm1_1>;
+def sub_vrm1_6 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_0>;
+def sub_vrm1_7 : ComposedSubRegIndex<sub_vrm2_3, sub_vrm1_1>;
} // Namespace = "RISCV"
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