[PATCH] D106176: [Scheduler] Treat weak edges uniformly at entry

[Joe Nash via Phabricator via llvm-commits]

Joe_Nash created this revision.
Joe_Nash added reviewers: sunfish, critson, fhahn.
Herald added subscribers: javed.absar, hiraditya.
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There is a bug where the assert CurCycle >= SU->getDepth() in
SchedulePostRATDList::ScheduleNodeTopDown will fire when an instruction has only
weak predecessors and would otherwise be available at the entry of a scheduling
dag. For all nodes which are not immediately available, we respect the depth
(which respects weak edges) and do not move nodes from pending to available
until the proper depth is met. This patch makes that consistent for entry
available nodes as well.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106176

Files:
  llvm/lib/CodeGen/PostRASchedulerList.cpp


Index: llvm/lib/CodeGen/PostRASchedulerList.cpp
===================================================================
--- llvm/lib/CodeGen/PostRASchedulerList.cpp
+++ llvm/lib/CodeGen/PostRASchedulerList.cpp
@@ -534,8 +534,13 @@
   for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
     // It is available if it has no predecessors.
     if (!SUnits[i].NumPredsLeft && !SUnits[i].isAvailable) {
-      AvailableQueue.push(&SUnits[i]);
-      SUnits[i].isAvailable = true;
+      if (SUnits[i].getDepth() > 0) {
+        assert(SUnits[i].WeakPredsLeft > 0 && "Expected a weak predecessor");
+        PendingQueue.push_back(&SUnits[i]);
+      } else {
+        AvailableQueue.push(&SUnits[i]);
+        SUnits[i].isAvailable = true;
+      }
     }
   }
 


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