[llvm] 9ad1a49 - Mips/GlobalISel: Use LLT form of getMachineMemOperand

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2021-07-16T11:41:32-04:00
New Revision: 9ad1a499562bf9f7bc9f5ef70664201f4e9d51c6

URL: https://github.com/llvm/llvm-project/commit/9ad1a499562bf9f7bc9f5ef70664201f4e9d51c6
DIFF: https://github.com/llvm/llvm-project/commit/9ad1a499562bf9f7bc9f5ef70664201f4e9d51c6.diff

LOG: Mips/GlobalISel: Use LLT form of getMachineMemOperand

NFC here since it's just using a scalar anyway.

Added: 
    

Modified: 
    llvm/lib/Target/Mips/MipsCallLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/Mips/MipsCallLowering.cpp b/llvm/lib/Target/Mips/MipsCallLowering.cpp
index d82df0c6b6f2..5c2549ee176b 100644
--- a/llvm/lib/Target/Mips/MipsCallLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsCallLowering.cpp
@@ -411,15 +411,16 @@ bool MipsCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
 
     for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) {
       MIRBuilder.getMBB().addLiveIn(ArgRegs[I]);
-
+      LLT RegTy = LLT::scalar(RegSize * 8);
       MachineInstrBuilder Copy =
-          MIRBuilder.buildCopy(LLT::scalar(RegSize * 8), Register(ArgRegs[I]));
+          MIRBuilder.buildCopy(RegTy, Register(ArgRegs[I]));
       FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true);
       MachinePointerInfo MPO = MachinePointerInfo::getFixedStack(MF, FI);
-      MachineInstrBuilder FrameIndex =
-          MIRBuilder.buildFrameIndex(LLT::pointer(MPO.getAddrSpace(), 32), FI);
+
+      const LLT PtrTy = LLT::pointer(MPO.getAddrSpace(), 32);
+      auto FrameIndex = MIRBuilder.buildFrameIndex(PtrTy, FI);
       MachineMemOperand *MMO = MF.getMachineMemOperand(
-          MPO, MachineMemOperand::MOStore, RegSize, Align(RegSize));
+          MPO, MachineMemOperand::MOStore, RegTy, Align(RegSize));
       MIRBuilder.buildStore(Copy, FrameIndex, *MMO);
     }
   }