[PATCH] D106142: AArch64: support 8 & 16-bit atomic operations in GlobalISel

[Tim Northover via Phabricator via llvm-commits]

t.p.northover created this revision.
t.p.northover added a reviewer: paquette.
Herald added subscribers: danielkiss, jfb, hiraditya, kristof.beyls, rovka, mcrosier.
t.p.northover requested review of this revision.
Herald added a project: LLVM.

We have SelectionDAG patterns for 8 & 16-bit atomic operations, but they assume the value types will have been legalized to 32-bits. So this adds the ability to widen them to both AArch64 & generic GISel infrastructure.


https://reviews.llvm.org/D106142

Files:
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir
  llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir

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