[PATCH] D105854: [PowerPC] Inefficient register allocation of ACC registers results in many copies.

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.

LGTM other than a couple of comment nits.
Also, since this affects target independent code in the register allocator, please hold off on committing in case @qcolombet has concerns regarding the changes to the register allocator.



================
Comment at: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:492
+      VirtReg, Order, Hints, MF, VRM, Matrix);
+  for (MachineInstr &Use : MRI->reg_nodbg_instructions(VirtReg)) {
+    const MachineOperand *ResultOp = nullptr;
----------------
```
// We are interested in instructions that copy values to ACC/UACC.
// The copy into UACC will be simply a COPY to a subreg so we
// want to allocate the corresponding physical subreg for the source.
// The copy into ACC will be a BUILD_UACC so we want to allocate
// the same number UACC for the source.
```


================
Comment at: llvm/lib/Target/PowerPC/PPCRegisterInfo.td:466
+  // to assign these registers first. This is done because the ACC registers
+  // must represent 4 advacent vector registers. For example ACC1 must be
+  // V4, V5, V6, V7. The value here must be at least 32 as we want to allocate
----------------
s/advacent/adjacent

Also, V4-V7 are VMX registers. The ACC registers overlap the low VSX registers (the FPR's). So that should probably say `VS4 - VS7` rather than `V4, V5, V6, V7`.


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  https://reviews.llvm.org/D105854/new/

https://reviews.llvm.org/D105854