[PATCH] D106134: [RISCV] Make VLEN no greater than 65536.
Jianjian Guan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 16 02:09:37 PDT 2021
jacquesguan created this revision.
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Add constraint of VLEN for RVV v1.0-rc
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D106134
Files:
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
llvm/lib/Target/RISCV/RISCVSubtarget.cpp
Index: llvm/lib/Target/RISCV/RISCVSubtarget.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -109,30 +109,32 @@
assert(hasStdExtV() && "Tried to get vector length without V support!");
if (RVVVectorBitsMax == 0)
return 0;
- assert(RVVVectorBitsMax >= 128 && isPowerOf2_32(RVVVectorBitsMax) &&
- "V extension requires vector length to be at least 128 and a power of "
- "2!");
+ assert(RVVVectorBitsMax >= 128 && RVVVectorBitsMax <= 65536 &&
+ isPowerOf2_32(RVVVectorBitsMax) &&
+ "V extension requires vector length to be in the range of 128 to "
+ "65536 and a power of 2!");
assert(RVVVectorBitsMax >= RVVVectorBitsMin &&
"Minimum V extension vector length should not be larger than its "
"maximum!");
unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax);
- return PowerOf2Floor(Max < 128 ? 0 : Max);
+ return PowerOf2Floor((Max < 128 || Max > 65536) ? 0 : Max);
}
unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
assert(hasStdExtV() &&
"Tried to get vector length without V extension support!");
assert((RVVVectorBitsMin == 0 ||
- (RVVVectorBitsMin >= 128 && isPowerOf2_32(RVVVectorBitsMin))) &&
- "V extension requires vector length to be at least 128 and a power of "
- "2!");
+ (RVVVectorBitsMin >= 128 && RVVVectorBitsMax <= 65536 &&
+ isPowerOf2_32(RVVVectorBitsMin))) &&
+ "V extension requires vector length to be in the range of 128 to "
+ "65536 and a power of 2!");
assert((RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == 0) &&
"Minimum V extension vector length should not be larger than its "
"maximum!");
unsigned Min = RVVVectorBitsMin;
if (RVVVectorBitsMax != 0)
Min = std::min(RVVVectorBitsMin, RVVVectorBitsMax);
- return PowerOf2Floor(Min < 128 ? 0 : Min);
+ return PowerOf2Floor((Min < 128 || Min > 65536) ? 0 : Min);
}
unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -285,8 +285,7 @@
// Vector type mapping to LLVM types.
//
-// Though the V extension allows that VLEN be as small as 8,
-// this approach assumes that VLEN>=64.
+// The V vector extension requires that VLEN >= 128 and <= 65536.
// Additionally, the only supported ELEN values are 32 and 64,
// thus `vscale` can be defined as VLEN/64,
// allowing the same types with either ELEN value.
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