[llvm] f5917e0 - [TableGen] Allow isAllocatable inheritence from any superclass

[Carl Ritson via llvm-commits]

Author: Carl Ritson
Date: 2021-07-16T13:02:24+09:00
New Revision: f5917e0312edacf1fe4cfebc532e3a78c854adee

URL: https://github.com/llvm/llvm-project/commit/f5917e0312edacf1fe4cfebc532e3a78c854adee
DIFF: https://github.com/llvm/llvm-project/commit/f5917e0312edacf1fe4cfebc532e3a78c854adee.diff

LOG: [TableGen] Allow isAllocatable inheritence from any superclass

When setting Allocatable on a generated register class check all
superclasses and set Allocatable true if any superclass is
allocatable.

Without this change generated register classes based on an
allocatable class may end up unallocatable due to the topological
inheritance order.

This change primarily effects AMDGPU backend; however, there are
a few changes in MIPs GlobalISel register constraints as a result.

Reviewed By: kparzysz

Differential Revision: https://reviews.llvm.org/D105967

Added: 
    

Modified: 
    llvm/utils/TableGen/CodeGenRegisters.cpp

Removed: 
    


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diff  --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/CodeGenRegisters.cpp
index db15bac9c3f8..930b7742103e 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -833,7 +833,10 @@ void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) {
   Namespace = Super.Namespace;
   VTs = Super.VTs;
   CopyCost = Super.CopyCost;
-  Allocatable = Super.Allocatable;
+  // Check for allocatable superclasses.
+  Allocatable = any_of(SuperClasses, [&](const CodeGenRegisterClass *S) {
+    return S->Allocatable;
+  });
   AltOrderSelect = Super.AltOrderSelect;
   AllocationPriority = Super.AllocationPriority;
   GeneratePressureSet |= Super.GeneratePressureSet;