[PATCH] D105730: [SLP] match logical and/or as reduction candidates

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


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Comment at: llvm/test/Transforms/SLPVectorizer/X86/reduction-logical.ll:187
+; CHECK-NEXT:    [[TMP10:%.*]] = and i1 [[TMP9]], [[D2]]
+; CHECK-NEXT:    [[S7:%.*]] = select i1 [[TMP10]], i1 [[D3]], i1 false
 ; CHECK-NEXT:    ret i1 [[S7]]
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efriedma wrote:
> Alive2 apparently doesn't like this.  See https://web.ist.utl.pt/nuno.lopes/alive2/index.php?hash=047d8ce24c780675&test=Transforms%2FSLPVectorizer%2FX86%2Freduction-logical.ll
Yes - @nlopes just noted this on the commit page/thread too ( https://reviews.llvm.org/rG25ee55c0baff ).
I didn't notice that we had replaced select insts with logic, so we either need to prevent, restore, or freeze our way out of that.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105730/new/

https://reviews.llvm.org/D105730