[PATCH] D106072: [AMDGPU][MC] Added missing isCall/isBranch flags

[Dmitry Preobrazhensky via Phabricator via llvm-commits]

dp created this revision.
dp added reviewers: foad, rampitec.
Herald added subscribers: kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl, arsenm.
dp requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.

These flags are required for Comgr to annotate jump targets.
This is a supplement for D99955 <https://reviews.llvm.org/D99955>.


https://reviews.llvm.org/D106072

Files:
  llvm/lib/Target/AMDGPU/SOPInstructions.td


Index: llvm/lib/Target/AMDGPU/SOPInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -1655,13 +1655,18 @@
 }
 
 defm S_VERSION              : SOPK_Real32_gfx10<0x001>;
-defm S_CALL_B64             : SOPK_Real32_gfx10<0x016>;
 defm S_WAITCNT_VSCNT        : SOPK_Real32_gfx10<0x017>;
 defm S_WAITCNT_VMCNT        : SOPK_Real32_gfx10<0x018>;
 defm S_WAITCNT_EXPCNT       : SOPK_Real32_gfx10<0x019>;
 defm S_WAITCNT_LGKMCNT      : SOPK_Real32_gfx10<0x01a>;
+
+let isCall = 1 in
+defm S_CALL_B64             : SOPK_Real32_gfx10<0x016>;
+
+let isBranch = 1 in {
 defm S_SUBVECTOR_LOOP_BEGIN : SOPK_Real32_gfx10<0x01b>;
 defm S_SUBVECTOR_LOOP_END   : SOPK_Real32_gfx10<0x01c>;
+}
 
 //===----------------------------------------------------------------------===//
 // SOPK - GFX6, GFX7.
@@ -2011,6 +2016,7 @@
 def S_SETREG_IMM32_B32_vi  : SOPK_Real64<0x14, S_SETREG_IMM32_B32>,
                              Select_vi<S_SETREG_IMM32_B32.Mnemonic>;
 
+let isCall = 1 in
 def S_CALL_B64_vi          : SOPK_Real_vi <0x15, S_CALL_B64>;
 
 //===----------------------------------------------------------------------===//


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