[PATCH] D105847: [AArch64] Prepare for changes to STEP_VECTOR.

[David Sherwood via Phabricator via llvm-commits]

david-arm added a comment.

The changes to the existing patterns look sensible to me, but maybe someone else can take a look at the new patterns?



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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:4924
+            (!cast<Instruction>(NAME # "_D") simm5_64b:$imm5, (!cast<Instruction>("MOVi64imm") imm:$imm))>;
+  def : Pat<(add (nxv2i64 (step_vector_oneuse (i64 !cast<ImmLeaf>("i64imm_32bit"):$imm))), (nxv2i64 (AArch64dup(simm5_64b:$imm5)))),
+            (!cast<Instruction>(NAME # "_D") simm5_64b:$imm5, (SUBREG_TO_REG (i64 0), (!cast<Instruction>("MOVi32imm") (!cast<SDNodeXForm>("trunc_imm") imm:$imm)), sub_32))>;
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To be honest I find it a bit difficult to work out what's going on here and what pattern it's matching. Is it possible to point to a specific test that's defending this?


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105847/new/

https://reviews.llvm.org/D105847