[PATCH] D105872: [PowerPC] prepare more loop load/store instructions

[ChenZheng via Phabricator via llvm-commits]

shchenz added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/lsr-profitable-chain.ll:9
 ; CHECK-NEXT:    cmpd 5, 7
+; CHECK-NEXT:    std 19, -104(1) # 8-byte Folded Spill
+; CHECK-NEXT:    std 20, -96(1) # 8-byte Folded Spill
----------------
shchenz wrote:
> This would be a FIXME. This series of patches will common out multiples chains for load/stores even with same common base and with non-const increment.
> 
> This patch is the first one to make pass PPCLoopInstFormPrep prepare load/stores with non-const increment.
> 
> The next patches will be: select multiple common addresses which can make the different chains(based on different common addresses) reuse same offsets, thus we can reduce register pressure.
Another note for this regression, it does not break the case's original intention. Even with the register pressure regression, the load instructions in the nested loop are all still with dform.


Repository:
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  https://reviews.llvm.org/D105872/new/

https://reviews.llvm.org/D105872