[PATCH] D105572: [AArch64][SME] Add load and store instructions

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes updated this revision to Diff 358561.
c-rhodes edited the summary of this revision.
c-rhodes added a comment.

- Update enum value of FPR64 regclass in `llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir`, since the old value is now referencing `WSeqPairsClass_with_sube32_in_MatrixIndexGPR32_12_15`.
- Tweaked `isMatrixRegOperand` to return NearMatch to improve diagnostics.
- Added diagnostics tests for load/store instructions where the matrix operand is valid (i.e. it can be parsed) but doesn't match what's expected for the instruction.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105572/new/

https://reviews.llvm.org/D105572

Files:
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
  llvm/lib/Target/AArch64/AArch64RegisterInfo.td
  llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
  llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
  llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
  llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
  llvm/lib/Target/AArch64/SMEInstrFormats.td
  llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
  llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
  llvm/test/CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir
  llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir
  llvm/test/MC/AArch64/SME/addha-diagnostics.s
  llvm/test/MC/AArch64/SME/ld1b-diagnostics.s
  llvm/test/MC/AArch64/SME/ld1b.s
  llvm/test/MC/AArch64/SME/ld1d-diagnostics.s
  llvm/test/MC/AArch64/SME/ld1d.s
  llvm/test/MC/AArch64/SME/ld1h-diagnostics.s
  llvm/test/MC/AArch64/SME/ld1h.s
  llvm/test/MC/AArch64/SME/ld1q-diagnostics.s
  llvm/test/MC/AArch64/SME/ld1q.s
  llvm/test/MC/AArch64/SME/ld1w-diagnostics.s
  llvm/test/MC/AArch64/SME/ld1w.s
  llvm/test/MC/AArch64/SME/st1b-diagnostics.s
  llvm/test/MC/AArch64/SME/st1b.s
  llvm/test/MC/AArch64/SME/st1d-diagnostics.s
  llvm/test/MC/AArch64/SME/st1d.s
  llvm/test/MC/AArch64/SME/st1h-diagnostics.s
  llvm/test/MC/AArch64/SME/st1h.s
  llvm/test/MC/AArch64/SME/st1q-diagnostics.s
  llvm/test/MC/AArch64/SME/st1q.s
  llvm/test/MC/AArch64/SME/st1w-diagnostics.s
  llvm/test/MC/AArch64/SME/st1w.s
  llvm/test/MC/AArch64/neon-diagnostics.s

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