[PATCH] D105953: [MachineVerifier] Diagnose invalid INSERT_SUBREGs

[Jon Roelofs via Phabricator via llvm-commits]

jroelofs created this revision.
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Herald added a subscriber: hiraditya.
jroelofs requested review of this revision.
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Herald added a subscriber: llvm-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D105953

Files:
  llvm/lib/CodeGen/MachineVerifier.cpp
  llvm/test/MachineVerifier/test_insert_subreg.mir


Index: llvm/test/MachineVerifier/test_insert_subreg.mir
===================================================================
--- /dev/null
+++ llvm/test/MachineVerifier/test_insert_subreg.mir
@@ -0,0 +1,34 @@
+#RUN: not --crash llc -march=aarch64 -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
+# REQUIRES: aarch64-registered-target
+
+---
+name:            test_insert_subreg
+legalized:       true
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+liveins:
+body:             |
+  bb.0:
+    liveins: $s0, $h1
+
+    %0:fpr32 = COPY $s0
+
+    ; CHECK: *** Bad machine code: INSERT_SUBREG expected matching subreg size for operand 2 ***
+    %1:fpr128 = IMPLICIT_DEF
+    %2:fpr128 = INSERT_SUBREG %1:fpr128, %0:fpr32, %subreg.hsub
+
+    ; CHECK: *** Bad machine code: INSERT_SUBREG expected matching subreg size for operand 2 ***
+    %3:fpr128 = IMPLICIT_DEF
+    %4:fpr128 = INSERT_SUBREG %3:fpr128, %0:fpr32, %subreg.dsub
+
+    ; CHECK-NOT: *** Bad machine code:
+    %7:fpr128 = IMPLICIT_DEF
+    %8:fpr128 = INSERT_SUBREG %7:fpr128, %0:fpr32, %subreg.ssub
+
+    ; CHECK: *** Bad machine code: INSERT_SUBREG did not expect subreg size >= superreg size ***
+    %9:fpr16 = COPY $h1
+    %10:fpr16 = IMPLICIT_DEF
+    %11:fpr16 = INSERT_SUBREG %10:fpr16, %9:fpr16, %subreg.hsub
+
+...
Index: llvm/lib/CodeGen/MachineVerifier.cpp
===================================================================
--- llvm/lib/CodeGen/MachineVerifier.cpp
+++ llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1782,6 +1782,23 @@
 
     // TODO: verify we have properly encoded deopt arguments
   } break;
+  case TargetOpcode::INSERT_SUBREG: {
+    const auto &TRI = MRI->getTargetRegisterInfo();
+    unsigned InsertedSize =
+        TRI->getRegSizeInBits(MI->getOperand(2).getReg(), *MRI);
+    unsigned SubRegSize = TRI->getSubRegIdxSize(MI->getOperand(3).getImm());
+    if (InsertedSize != SubRegSize) {
+      report("INSERT_SUBREG expected matching subreg size for operand 2", MI);
+      break;
+    }
+
+    unsigned SuperRegSize =
+        TRI->getRegSizeInBits(MI->getOperand(1).getReg(), *MRI);
+    if (SuperRegSize <= SubRegSize) {
+      report("INSERT_SUBREG did not expect subreg size >= superreg size", MI);
+      break;
+    }
+  } break;
   }
 }
 


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