[PATCH] D105913: [AArch64][GlobalISel] Legalize load <2 x i16>
Jon Roelofs via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 13 11:13:15 PDT 2021
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGeba638dbbb77: [AArch64][GlobalISel] Legalize load <2 x i16> (authored by jroelofs).
Changed prior to commit:
https://reviews.llvm.org/D105913?vs=358339&id=358358#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105913/new/
https://reviews.llvm.org/D105913
Files:
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
Index: llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
===================================================================
--- llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
+++ llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
@@ -565,3 +565,26 @@
RET_ReallyLR
...
+---
+name: load_2xi16
+tracksRegLiveness: true
+body: |
+ bb.1:
+ liveins: $s0, $x0
+
+ ; CHECK-LABEL: name: load_2xi16
+ ; CHECK: liveins: $s0, $x0
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16), align 4)
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
+ ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
+ ; CHECK: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2)
+ ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[LOAD]](s16), [[LOAD1]](s16)
+ ; CHECK: $s0 = COPY [[BUILD_VECTOR]](<2 x s16>)
+ ; CHECK: RET_ReallyLR
+ %0:_(p0) = COPY $x0
+ %1(<2 x s16>) = G_LOAD %0(p0) :: (load (<2 x s16>))
+ $s0 = COPY %1:_(<2 x s16>)
+ RET_ReallyLR
+
+...
Index: llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -311,7 +311,8 @@
.clampMaxNumElements(0, s16, 8)
.clampMaxNumElements(0, s32, 4)
.clampMaxNumElements(0, s64, 2)
- .customIf(IsPtrVecPred);
+ .customIf(IsPtrVecPred)
+ .scalarizeIf(typeIs(0, v2s16), 0);
getActionDefinitionsBuilder(G_STORE)
.legalForTypesWithMemDesc({{s8, p0, s8, 8},
@@ -651,6 +652,7 @@
getActionDefinitionsBuilder(G_BUILD_VECTOR)
.legalFor({{v8s8, s8},
{v16s8, s8},
+ {v2s16, s16},
{v4s16, s16},
{v8s16, s16},
{v2s32, s32},
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