[llvm] fb44c32 - AMDGPU: Promote signext/zeroext i16 shader returns

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2021-07-13T11:04:51-04:00
New Revision: fb44c3223e0c36e969762dd182b4992061b455d3

URL: https://github.com/llvm/llvm-project/commit/fb44c3223e0c36e969762dd182b4992061b455d3
DIFF: https://github.com/llvm/llvm-project/commit/fb44c3223e0c36e969762dd182b4992061b455d3.diff

LOG: AMDGPU: Promote signext/zeroext i16 shader returns

This makes them consistent with all the other return convention
handling. If we don't do this, we lose the sext/zext flag if treated
as a full assignment, which complicates a future GlobalISel patch.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
index 43cb4bfb4c5c..90b52395b76c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
@@ -107,6 +107,7 @@ def CC_SI_SHADER : CallingConv<[
 ]>;
 
 def RetCC_SI_Shader : CallingConv<[
+  CCIfType<[i1, i16], CCIfExtend<CCPromoteToType<i32>>>,
   CCIfType<[i32, i16] , CCAssignToReg<[
     SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
     SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15,