[llvm] 77a608d - GlobalISel: Remove getIntrinsicID utility function

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2021-07-13T11:04:10-04:00
New Revision: 77a608d9de472766fcab51412100764e534ceaf9

URL: https://github.com/llvm/llvm-project/commit/77a608d9de472766fcab51412100764e534ceaf9
DIFF: https://github.com/llvm/llvm-project/commit/77a608d9de472766fcab51412100764e534ceaf9.diff

LOG: GlobalISel: Remove getIntrinsicID utility function

This is redundant with a method directly on MachineInstr

Added: 
    

Modified: 
    llvm/include/llvm/CodeGen/GlobalISel/Utils.h
    llvm/lib/CodeGen/GlobalISel/Utils.cpp
    llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
index 5bb36ad0a477b..64a9908677eb3 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h
@@ -384,9 +384,5 @@ int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP);
 bool shouldOptForSize(const MachineBasicBlock &MBB, ProfileSummaryInfo *PSI,
                       BlockFrequencyInfo *BFI);
 
-/// \returns the intrinsic ID for a G_INTRINSIC or G_INTRINSIC_W_SIDE_EFFECTS
-/// instruction \p MI.
-unsigned getIntrinsicID(const MachineInstr &MI);
-
 } // End namespace llvm.
 #endif

diff  --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index 73e42927f8e63..31b8347a0aebb 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -998,12 +998,3 @@ bool llvm::shouldOptForSize(const MachineBasicBlock &MBB,
   return F.hasOptSize() || F.hasMinSize() ||
          llvm::shouldOptimizeForSize(MBB.getBasicBlock(), PSI, BFI);
 }
-
-unsigned llvm::getIntrinsicID(const MachineInstr &MI) {
-#ifndef NDEBUG
-  unsigned Opc = MI.getOpcode();
-  assert(Opc == TargetOpcode::G_INTRINSIC ||
-         Opc == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS);
-#endif
-  return MI.getOperand(MI.getNumExplicitDefs()).getIntrinsicID();
-}

diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index 705654d01692e..e16e7d71329fa 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -487,7 +487,7 @@ bool AArch64RegisterBankInfo::hasFPConstraints(const MachineInstr &MI,
                                                const TargetRegisterInfo &TRI,
                                                unsigned Depth) const {
   unsigned Op = MI.getOpcode();
-  if (Op == TargetOpcode::G_INTRINSIC && isFPIntrinsic(getIntrinsicID(MI)))
+  if (Op == TargetOpcode::G_INTRINSIC && isFPIntrinsic(MI.getIntrinsicID()))
     return true;
 
   // Do we have an explicit floating point instruction?
@@ -945,7 +945,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case TargetOpcode::G_INTRINSIC: {
     // Check if we know that the intrinsic has any constraints on its register
     // banks. If it does, then update the mapping accordingly.
-    unsigned ID = getIntrinsicID(MI);
+    unsigned ID = MI.getIntrinsicID();
     unsigned Idx = 0;
     if (!isFPIntrinsic(ID))
       break;