[PATCH] D105570: [AArch64][SME] Add matrix register definitions and parsing support

[David Sherwood via Phabricator via llvm-commits]

david-arm accepted this revision.
david-arm added a comment.
This revision is now accepted and ready to land.

LGTM! Perhaps fix a couple of formatting issues before merging?



================
Comment at: llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp:891
+  O << getRegisterName(RegOp.getReg());
+  switch(EltSize) {
+  case 0: break;
----------------
nit: Perhaps it's worth fixing the formatting here? I looked in this file and there seems to be a mixture of styles so it's not obvious we should stick to an older style.


================
Comment at: llvm/unittests/Target/AArch64/MatrixRegisterAliasing.cpp:22
+
+  return std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine*>(
+      TheTarget->createTargetMachine(TT, CPU, FS, TargetOptions(), None, None,
----------------
nit: Maybe fix formatting here?


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  https://reviews.llvm.org/D105570/new/

https://reviews.llvm.org/D105570