[llvm] 3cee36c - [X86][SSE] X86ISD::FSETCC nodes (cmpss/cmpsd) return a 0/-1 allbits signbits result (REAPPLIED)

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-07-13T12:31:09+01:00
New Revision: 3cee36c5acdb292c331818c553bfb8e5abbdb95e

URL: https://github.com/llvm/llvm-project/commit/3cee36c5acdb292c331818c553bfb8e5abbdb95e
DIFF: https://github.com/llvm/llvm-project/commit/3cee36c5acdb292c331818c553bfb8e5abbdb95e.diff

LOG: [X86][SSE] X86ISD::FSETCC nodes (cmpss/cmpsd) return a 0/-1 allbits signbits result (REAPPLIED)

Annoyingly, i686 cmpsd handling still fails to remove the unnecessary neg(and(x,1))

Reapplied rGe4aa6ad13216 with fix for intrinsic variants of the opcode which uses a vector return type

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/known-signbits-vector.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 0410a6923310..8697588faa75 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -34922,6 +34922,13 @@ unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
     return ShiftVal.uge(VTBits) ? VTBits : ShiftVal.getZExtValue();
   }
 
+  case X86ISD::FSETCC:
+    // cmpss/cmpsd return zero/all-bits result values in the bottom element.
+    if (VT == MVT::f32 || VT == MVT::f64 ||
+        ((VT == MVT::v4f32 || VT == MVT::v2f64) && DemandedElts == 1))
+      return VTBits;
+    break;
+
   case X86ISD::PCMPGT:
   case X86ISD::PCMPEQ:
   case X86ISD::CMPP:

diff  --git a/llvm/test/CodeGen/X86/known-signbits-vector.ll b/llvm/test/CodeGen/X86/known-signbits-vector.ll
index b63d458f2065..e18819ae11f2 100644
--- a/llvm/test/CodeGen/X86/known-signbits-vector.ll
+++ b/llvm/test/CodeGen/X86/known-signbits-vector.ll
@@ -666,16 +666,12 @@ define i32 @signbits_cmpss(float %0, float %1) {
 ; X86-NEXT:    vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
 ; X86-NEXT:    vcmpeqss {{[0-9]+}}(%esp), %xmm0, %xmm0
 ; X86-NEXT:    vmovd %xmm0, %eax
-; X86-NEXT:    andl $1, %eax
-; X86-NEXT:    negl %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: signbits_cmpss:
 ; X64:       # %bb.0:
 ; X64-NEXT:    vcmpeqss %xmm1, %xmm0, %xmm0
 ; X64-NEXT:    vmovd %xmm0, %eax
-; X64-NEXT:    andl $1, %eax
-; X64-NEXT:    negl %eax
 ; X64-NEXT:    retq
   %3 = fcmp oeq float %0, %1
   %4 = sext i1 %3 to i32
@@ -687,7 +683,6 @@ define i32 @signbits_cmpss_int(<4 x float> %0, <4 x float> %1) {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vcmpeqss %xmm1, %xmm0, %xmm0
 ; CHECK-NEXT:    vextractps $0, %xmm0, %eax
-; CHECK-NEXT:    sarl $31, %eax
 ; CHECK-NEXT:    ret{{[l|q]}}
   %3 = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %0, <4 x float> %1, i8 0)
   %4 = bitcast <4 x float> %3 to <4 x i32>
@@ -712,8 +707,6 @@ define i64 @signbits_cmpsd(double %0, double %1) {
 ; X64:       # %bb.0:
 ; X64-NEXT:    vcmpeqsd %xmm1, %xmm0, %xmm0
 ; X64-NEXT:    vmovq %xmm0, %rax
-; X64-NEXT:    andl $1, %eax
-; X64-NEXT:    negq %rax
 ; X64-NEXT:    retq
   %3 = fcmp oeq double %0, %1
   %4 = sext i1 %3 to i64
@@ -725,7 +718,6 @@ define i64 @signbits_cmpsd_int(<2 x double> %0, <2 x double> %1) {
 ; X86:       # %bb.0:
 ; X86-NEXT:    vcmpeqsd %xmm1, %xmm0, %xmm0
 ; X86-NEXT:    vextractps $1, %xmm0, %eax
-; X86-NEXT:    sarl $31, %eax
 ; X86-NEXT:    movl %eax, %edx
 ; X86-NEXT:    retl
 ;
@@ -733,7 +725,6 @@ define i64 @signbits_cmpsd_int(<2 x double> %0, <2 x double> %1) {
 ; X64:       # %bb.0:
 ; X64-NEXT:    vcmpeqsd %xmm1, %xmm0, %xmm0
 ; X64-NEXT:    vmovq %xmm0, %rax
-; X64-NEXT:    sarq $63, %rax
 ; X64-NEXT:    retq
   %3 = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %0, <2 x double> %1, i8 0)
   %4 = bitcast <2 x double> %3 to <2 x i64>