[PATCH] D105760: [AMDGPU] Handle s_branch to another section.

[Hafiz Abid Qadeer via Phabricator via llvm-commits]

abidh updated this revision to Diff 358207.
abidh added a comment.

Remove else after the return.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105760/new/

https://reviews.llvm.org/D105760

Files:
  llvm/docs/AMDGPUUsage.rst
  llvm/include/llvm/BinaryFormat/ELFRelocs/AMDGPU.def
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
  llvm/test/MC/AMDGPU/reloc.s
  llvm/test/Object/AMDGPU/elf64-relocs.yaml


Index: llvm/test/Object/AMDGPU/elf64-relocs.yaml
===================================================================
--- llvm/test/Object/AMDGPU/elf64-relocs.yaml
+++ llvm/test/Object/AMDGPU/elf64-relocs.yaml
@@ -16,6 +16,7 @@
 # CHECK:     0x20 R_AMDGPU_REL32_LO       - 0x0
 # CHECK:     0x22 R_AMDGPU_REL32_HI       - 0x0
 # CHECK:     0x24 R_AMDGPU_RELATIVE64     - 0x0
+# CHECK:     0x26 R_AMDGPU_REL16          - 0x0
 # CHECK:   }
 # CHECK: ]
 
@@ -62,6 +63,8 @@
         Type:            R_AMDGPU_REL32_HI
       - Offset:          0x24
         Type:            R_AMDGPU_RELATIVE64
+      - Offset:          0x26
+        Type:            R_AMDGPU_REL16
 
 Symbols:
   - Name:            .text
Index: llvm/test/MC/AMDGPU/reloc.s
===================================================================
--- llvm/test/MC/AMDGPU/reloc.s
+++ llvm/test/MC/AMDGPU/reloc.s
@@ -9,6 +9,7 @@
 // CHECK: R_AMDGPU_GOTPCREL32_HI global_var2
 // CHECK: R_AMDGPU_REL32_LO global_var3
 // CHECK: R_AMDGPU_REL32_HI global_var4
+// CHECK: R_AMDGPU_REL16 .text.unlikely
 // CHECK: R_AMDGPU_ABS32 var
 // CHECK: }
 // CHECK: .rel.data {
@@ -25,6 +26,11 @@
   s_mov_b32 s4, global_var2 at gotpcrel32@hi
   s_mov_b32 s5, global_var3 at rel32@lo
   s_mov_b32 s6, global_var4 at rel32@hi
+  s_branch cold
+
+  .section .text.unlikely
+cold:
+  s_add_i32 s15, s15, 1
 
 .globl global_var0
 .globl global_var1
Index: llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
+++ llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp
@@ -80,9 +80,12 @@
     const auto *SymA = Target.getSymA();
     assert(SymA);
 
-    Ctx.reportError(Fixup.getLoc(),
-                    Twine("undefined label '") + SymA->getSymbol().getName() + "'");
-    return ELF::R_AMDGPU_NONE;
+    if (SymA->getSymbol().isUndefined()) {
+      Ctx.reportError(Fixup.getLoc(), Twine("undefined label '") +
+                                          SymA->getSymbol().getName() + "'");
+      return ELF::R_AMDGPU_NONE;
+    }
+    return ELF::R_AMDGPU_REL16;
   }
 
   llvm_unreachable("unhandled relocation type");
Index: llvm/include/llvm/BinaryFormat/ELFRelocs/AMDGPU.def
===================================================================
--- llvm/include/llvm/BinaryFormat/ELFRelocs/AMDGPU.def
+++ llvm/include/llvm/BinaryFormat/ELFRelocs/AMDGPU.def
@@ -15,3 +15,4 @@
 ELF_RELOC(R_AMDGPU_REL32_LO,      10)
 ELF_RELOC(R_AMDGPU_REL32_HI,      11)
 ELF_RELOC(R_AMDGPU_RELATIVE64,    13)
+ELF_RELOC(R_AMDGPU_REL16,         14)
Index: llvm/docs/AMDGPUUsage.rst
===================================================================
--- llvm/docs/AMDGPUUsage.rst
+++ llvm/docs/AMDGPUUsage.rst
@@ -1574,6 +1574,7 @@
      ``R_AMDGPU_REL32_HI``      Static  11     ``word32``  (S + A - P) >> 32
      *reserved*                         12
      ``R_AMDGPU_RELATIVE64``    Dynamic 13     ``word64``  B + A
+     ``R_AMDGPU_REL16``         Static  14     ``word16``  ((S + A - P) - 4) / 4
      ========================== ======= =====  ==========  ==============================
 
 ``R_AMDGPU_ABS32_LO`` and ``R_AMDGPU_ABS32_HI`` are only supported by


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