[PATCH] D105875: [RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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Some microarchitectures treat rs1=x1/x5 on jalr as a hint to pop
the return-address stack. We should avoid using x5 on jalr
instructions since we aren't using x5 as an alternate link register.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D105875

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/CodeGen/RISCV/calls.ll
  llvm/test/CodeGen/RISCV/tail-calls.ll

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