[PATCH] D105854: [PowerPC] Inefficient scheduling of ACC registers results in many copies.

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp created this revision.
stefanp added reviewers: jsji, nemanjai, lei.
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ACC registers are a combination of four consecutive vector registers.
If the vector registers are assigned first this often forces a number
of copies to appear just before the ACC regsiter is created. If the ACC
regsiter is assigned first then fewer copies are generated when the vector
registers are assigned.

This patch tries to force the scheduler to assign the ACC registers first
and then the UACC regsiters and then the vector pair regsisters. It does this
by changing the priority of the register classes.

This patch also adds hints to help the scheduler assugn UACC regsiters from
known ACC regsiters and vector pair regsiters from known UACC regsires.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D105854

Files:
  llvm/include/llvm/CodeGen/TargetRegisterInfo.h
  llvm/lib/CodeGen/RegAllocGreedy.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.h
  llvm/lib/Target/PowerPC/PPCRegisterInfo.td
  llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll
  llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
  llvm/test/CodeGen/PowerPC/mma-outer-product.ll
  llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll
  llvm/test/CodeGen/PowerPC/ppc64-acc-schedule.ll

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