[PATCH] D105853: [ISel] Expand saddsat and ssubsat via asr and xor

[Dave Green via Phabricator via llvm-commits]

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This changes the lowering of saddsat and ssubsat so that instead of using

  r,o = saddo x, y
  c = setcc r < 0
  s = c ? INTMAX : INTMIN
  ret o ? s : r

into using asr and xor to materialize the INTMAX/INTMIN constants:

  r,o = saddo x, y
  s = ashr r, BW-1
  x = xor s, INTMIN
  ret o ? x : r


https://alive2.llvm.org/ce/z/TYufgD

This seems to reduce the instruction count in most testcases across most architectures.


https://reviews.llvm.org/D105853

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AArch64/sadd_sat.ll
  llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
  llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
  llvm/test/CodeGen/AArch64/ssub_sat.ll
  llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
  llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
  llvm/test/CodeGen/AMDGPU/saddsat.ll
  llvm/test/CodeGen/AMDGPU/ssubsat.ll
  llvm/test/CodeGen/ARM/qdadd.ll
  llvm/test/CodeGen/ARM/sadd_sat.ll
  llvm/test/CodeGen/ARM/sadd_sat_plus.ll
  llvm/test/CodeGen/ARM/ssub_sat.ll
  llvm/test/CodeGen/ARM/ssub_sat_plus.ll
  llvm/test/CodeGen/PowerPC/sat-add.ll
  llvm/test/CodeGen/RISCV/sadd_sat.ll
  llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
  llvm/test/CodeGen/RISCV/ssub_sat.ll
  llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
  llvm/test/CodeGen/Thumb2/mve-saturating-arith.ll
  llvm/test/CodeGen/X86/combine-add-ssat.ll
  llvm/test/CodeGen/X86/sadd_sat.ll
  llvm/test/CodeGen/X86/sadd_sat_plus.ll
  llvm/test/CodeGen/X86/sadd_sat_vec.ll
  llvm/test/CodeGen/X86/ssub_sat.ll
  llvm/test/CodeGen/X86/ssub_sat_plus.ll
  llvm/test/CodeGen/X86/ssub_sat_vec.ll

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