[PATCH] D105633: [WIP] Improve code generation for vector_splice

[Caroline via Phabricator via llvm-commits]

CarolineConcatto updated this revision to Diff 358058.
CarolineConcatto added a comment.

- Address Sander's suggestion and use EXT when lane/Imm is bigger than 0
- and use INSR + LAST for lane/Imm equals to -1


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105633/new/

https://reviews.llvm.org/D105633

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll

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