[PATCH] D105840: [SelectionDAG][RISCV] Support @llvm.vscale.i64() on 32-bit targets.

[Craig Topper via Phabricator via llvm-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM



================
Comment at: llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll:55
+; RV32-NEXT:    srli a1, a0, 29
+; RV32-NEXT:    srli a0, a0, 3
+; RV32-NEXT:    slli a0, a0, 6
----------------
vlenb returns a multiple of 8 so we should be able to replace this srli 3 + slli 6 with just slli 3. But I think we have an ordering issue in visiting that prevents it from being simplified. That shouldn't block this patch though.


Repository:
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https://reviews.llvm.org/D105840