[llvm] ef49d92 - [PowerPC] Implement trap and conversion builtins for XL compatibility
Albion Fung via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 12 09:07:53 PDT 2021
Author: Albion Fung
Date: 2021-07-12T11:04:17-05:00
New Revision: ef49d925e2a788248473b847a0e51835c6ca854f
URL: https://github.com/llvm/llvm-project/commit/ef49d925e2a788248473b847a0e51835c6ca854f
DIFF: https://github.com/llvm/llvm-project/commit/ef49d925e2a788248473b847a0e51835c6ca854f.diff
LOG: [PowerPC] Implement trap and conversion builtins for XL compatibility
This patch implements trap and FP to and from double conversions. The builtins
generate code that mirror what is generated from the XL compiler. Intrinsics
are named conventionally with builtin_ppc, but are aliased to provide the same
builtin names as the XL compiler.
Differential Revision: https://reviews.llvm.org/D103668
Added:
clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-trap-64bit-only.c
clang/test/CodeGen/builtins-ppc-xlcompat-trap.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
Removed:
################################################################################
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def
index baaf5db9d1453..6a72cc089df7e 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -59,6 +59,18 @@ BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
+BUILTIN(__builtin_ppc_tdw, "vLLiLLiIUi", "")
+BUILTIN(__builtin_ppc_tw, "viiIUi", "")
+BUILTIN(__builtin_ppc_trap, "vi", "")
+BUILTIN(__builtin_ppc_trapd, "vLi", "")
+BUILTIN(__builtin_ppc_fcfid, "dd", "")
+BUILTIN(__builtin_ppc_fcfud, "dd", "")
+BUILTIN(__builtin_ppc_fctid, "dd", "")
+BUILTIN(__builtin_ppc_fctidz, "dd", "")
+BUILTIN(__builtin_ppc_fctiw, "dd", "")
+BUILTIN(__builtin_ppc_fctiwz, "dd", "")
+BUILTIN(__builtin_ppc_fctudz, "dd", "")
+BUILTIN(__builtin_ppc_fctuwz, "dd", "")
BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index e3c77b2e4450b..b77b4a38bc46f 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -112,6 +112,18 @@ static void defineXLCompatMacros(MacroBuilder &Builder) {
Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
+ Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
+ Builder.defineMacro("__tw", "__builtin_ppc_tw");
+ Builder.defineMacro("__trap", "__builtin_ppc_trap");
+ Builder.defineMacro("__trapd", "__builtin_ppc_trapd");
+ Builder.defineMacro("__fcfid", "__builtin_ppc_fcfid");
+ Builder.defineMacro("__fcfud", "__builtin_ppc_fcfud");
+ Builder.defineMacro("__fctid", "__builtin_ppc_fctid");
+ Builder.defineMacro("__fctidz", "__builtin_ppc_fctidz");
+ Builder.defineMacro("__fctiw", "__builtin_ppc_fctiw");
+ Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
+ Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
+ Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
}
/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 64d838d2cd74f..99621a226dea6 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3267,6 +3267,8 @@ static bool isPPC_64Builtin(unsigned BuiltinID) {
case PPC::BI__builtin_bpermd:
case PPC::BI__builtin_ppc_ldarx:
case PPC::BI__builtin_ppc_stdcx:
+ case PPC::BI__builtin_ppc_tdw:
+ case PPC::BI__builtin_ppc_trapd:
return true;
}
return false;
@@ -3347,6 +3349,9 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo &TI, unsigned BuiltinID,
return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
case PPC::BI__builtin_vsx_xxpermx:
return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
+ case PPC::BI__builtin_ppc_tw:
+ case PPC::BI__builtin_ppc_tdw:
+ return SemaBuiltinConstantArgRange(TheCall, 2, 0, 31);
#define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
case PPC::BI__builtin_##Name: \
return SemaBuiltinPPCMMACall(TheCall, Types);
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c b/clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
new file mode 100644
index 0000000000000..babc16fcd3a7e
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
@@ -0,0 +1,121 @@
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \
+// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc-unknown-aix \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-aix \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+
+extern double da;
+double test_fcfid() {
+ // CHECK-LABEL: test_fcfid
+ // CHECK-NEXT: entry:
+ // CHECK: double @llvm.ppc.fcfid(double %0)
+ return __builtin_ppc_fcfid(da);
+}
+
+double test_xl_fcfid() {
+ // CHECK-LABEL: test_xl_fcfid
+ // CHECK-NEXT: entry:
+ // CHECK: double @llvm.ppc.fcfid(double %0)
+ return __fcfid(da);
+}
+
+double test_fcfud() {
+ // CHECK-LABEL: test_fcfud
+ // CHECK-NEXT: entry:
+ // CHECK: double @llvm.ppc.fcfud(double %0)
+ return __builtin_ppc_fcfud(da);
+}
+
+double test_xl_fcfud() {
+ // CHECK-LABEL: test_xl_fcfud
+ // CHECK-NEXT: entry:
+ // CHECK: double @llvm.ppc.fcfud(double %0)
+ return __fcfud(da);
+}
+
+double test_fctid() {
+ // CHECK-LABEL: test_fctid
+ // CHECK-NEXT: entry:
+ // CHECK: double @llvm.ppc.fctid(double %0)
+ return __builtin_ppc_fctid(da);
+}
+
+double test_xl_fctid() {
+ // CHECK-LABEL: test_xl_fctid
+ // CHECK-NEXT: entry:
+ // CHECK: double @llvm.ppc.fctid(double %0)
+ return __fctid(da);
+}
+
+double test_fctidz() {
+ // CHECK-LABEL: test_fctidz
+ // CHECK-NEXT: entry:
+ // CHECK: double @llvm.ppc.fctidz(double %0)
+ return __builtin_ppc_fctidz(da);
+}
+
+double test_xl_fctidz() {
+ // CHECK-LABEL: test_xl_fctidz
+ // CHECK-NEXT: entry:
+ // CHECK: double @llvm.ppc.fctidz(double %0)
+ return __fctidz(da);
+}
+
+double test_fctiw() {
+ // CHECK-LABEL: test_fctiw
+ // CHECK-NEXT: entry:
+ // CHECK: double @llvm.ppc.fctiw(double %0)
+ return __builtin_ppc_fctiw(da);
+}
+
+double test_xl_fctiw() {
+ // CHECK-LABEL: test_xl_fctiw
+ // CHECK-NEXT: entry:
+ // CHECK: double @llvm.ppc.fctiw(double %0)
+ return __fctiw(da);
+}
+
+double test_fctiwz() {
+ // CHECK-LABEL: test_fctiwz
+ // CHECK-NEXT: entry:
+ // CHECK: double @llvm.ppc.fctiwz(double %0)
+ return __builtin_ppc_fctiwz(da);
+}
+
+double test_xl_fctiwz() {
+ // CHECK-LABEL: test_xl_fctiwz
+ // CHECK-NEXT: entry:
+ // CHECK: double @llvm.ppc.fctiwz(double %0)
+ return __fctiwz(da);
+}
+
+double test_fctudz() {
+ // CHECK-LABEL: test_fctudz
+ // CHECK-NEXT: entry:
+ // CHECK: double @llvm.ppc.fctudz(double %0)
+ return __builtin_ppc_fctudz(da);
+}
+
+double test_xl_fctudz() {
+ // CHECK-LABEL: test_xl_fctudz
+ // CHECK-NEXT: entry:
+ // CHECK: double @llvm.ppc.fctudz(double %0)
+ return __fctudz(da);
+}
+
+double test_fctuwz() {
+ // CHECK-LABEL: test_fctuwz
+ // CHECK-NEXT: entry:
+ // CHECK: double @llvm.ppc.fctuwz(double %0)
+ return __builtin_ppc_fctuwz(da);
+}
+
+double test_xl_fctuwz() {
+ // CHECK-LABEL: test_xl_fctuwz
+ // CHECK-NEXT: entry:
+ // CHECK: double @llvm.ppc.fctuwz(double %0)
+ return __fctuwz(da);
+}
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-error.c b/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
new file mode 100644
index 0000000000000..a4422299d7bee
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -0,0 +1,19 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
+// RUN: -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
+// RUN: -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc64-unknown-aix -fsyntax-only \
+// RUN: -Wall -Werror -verify %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix -fsyntax-only \
+// RUN: -Wall -Werror -verify %s
+
+extern long long lla, llb;
+extern int ia, ib;
+
+void test_trap(void) {
+#ifdef __PPC64__
+ __tdw(lla, llb, 50); //expected-error {{argument value 50 is outside the valid range [0, 31]}}
+#endif
+ __tw(ia, ib, 50); //expected-error {{argument value 50 is outside the valid range [0, 31]}}
+}
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-trap-64bit-only.c b/clang/test/CodeGen/builtins-ppc-xlcompat-trap-64bit-only.c
new file mode 100644
index 0000000000000..cea34c6bb3e9c
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-trap-64bit-only.c
@@ -0,0 +1,41 @@
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | \
+// RUN: FileCheck %s --check-prefixes=CHECK64
+// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \
+// RUN: -emit-llvm %s -o - -target-cpu pwr8 | \
+// RUN: FileCheck %s --check-prefixes=CHECK64
+// RUN: not %clang_cc1 -O2 -triple powerpc-unknown-aix \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 2>&1 | \
+// RUN: FileCheck %s -check-prefixes=CHECK32-ERROR
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-aix \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | \
+// RUN: FileCheck %s --check-prefixes=CHECK64
+
+extern long long lla, llb;
+extern double da;
+
+// tdw
+void test_xl_tdw(void) {
+// CHECK64: void @llvm.ppc.tdw(i64 %0, i64 %1, i32 1)
+// CHECK32-ERROR: error: this builtin is only available on 64-bit targets
+ __tdw(lla, llb, 1);
+}
+
+void test_tdw(void) {
+// CHECK64: void @llvm.ppc.tdw(i64 %0, i64 %1, i32 13)
+// CHECK32-ERROR: error: this builtin is only available on 64-bit targets
+ __builtin_ppc_tdw(lla, llb, 13);
+}
+
+// trapd
+void test_trapd(void) {
+// CHECK64: void @llvm.ppc.trapd(i64 %conv)
+// CHECK32-ERROR: error: this builtin is only available on 64-bit targets
+ __builtin_ppc_trapd(da);
+}
+
+void test_xl_trapd(void) {
+// CHECK64: void @llvm.ppc.trapd(i64 %conv)
+// CHECK32-ERROR: error: this builtin is only available on 64-bit targets
+ __trapd(da);
+}
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-trap.c b/clang/test/CodeGen/builtins-ppc-xlcompat-trap.c
new file mode 100644
index 0000000000000..5915daa34ce08
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-trap.c
@@ -0,0 +1,38 @@
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | \
+// RUN: FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \
+// RUN: -emit-llvm %s -o - -target-cpu pwr8 | \
+// RUN: FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc-unknown-aix \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | \
+// RUN: FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-aix \
+// RUN: -emit-llvm %s -o - -target-cpu pwr7 | \
+// RUN: FileCheck %s
+
+extern int ia, ib;
+
+// td
+void test_tw(void) {
+// CHECK: void @llvm.ppc.tw(i32 %0, i32 %1, i32 1)
+
+ __builtin_ppc_tw(ia, ib, 1);
+}
+
+void test_xl_tw(void) {
+// CHECK: void @llvm.ppc.tw(i32 %0, i32 %1, i32 1)
+
+ __tw(ia, ib, 1);
+}
+
+// trap
+void test_trap(void) {
+// CHECK: void @llvm.ppc.trap(i32 %0)
+ __builtin_ppc_trap(ia);
+}
+
+void test_xl_trap(void) {
+// CHECK: void @llvm.ppc.trap(i32 %0)
+ __trap(ia);
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index ad6a1e8d1a7a7..c02d964e5dd21 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -112,9 +112,45 @@ let TargetPrefix = "ppc" in { // All intrinsics start with "llvm.ppc.".
: GCCBuiltin<"__builtin_vsx_scalar_insert_exp_qp">,
Intrinsic <[llvm_f128_ty], [llvm_f128_ty, llvm_i64_ty], [IntrNoMem]>;
+ // Intrinsics defined to maintain XL compatibility
+ def int_ppc_tdw
+ : GCCBuiltin<"__builtin_ppc_tdw">,
+ Intrinsic <[], [llvm_i64_ty, llvm_i64_ty, llvm_i32_ty], [ImmArg<ArgIndex<2>>]>;
+ def int_ppc_tw
+ : GCCBuiltin<"__builtin_ppc_tw">,
+ Intrinsic <[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<2>>]>;
+ def int_ppc_trapd
+ : GCCBuiltin<"__builtin_ppc_trapd">,
+ Intrinsic <[], [llvm_i64_ty], []>;
+ def int_ppc_trap
+ : GCCBuiltin<"__builtin_ppc_trap">,
+ Intrinsic <[], [llvm_i32_ty], []>;
+ def int_ppc_fcfid
+ : GCCBuiltin<"__builtin_ppc_fcfid">,
+ Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+ def int_ppc_fcfud
+ : GCCBuiltin<"__builtin_ppc_fcfud">,
+ Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+ def int_ppc_fctid
+ : GCCBuiltin<"__builtin_ppc_fctid">,
+ Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+ def int_ppc_fctidz
+ : GCCBuiltin<"__builtin_ppc_fctidz">,
+ Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+ def int_ppc_fctiw
+ : GCCBuiltin<"__builtin_ppc_fctiw">,
+ Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+ def int_ppc_fctiwz
+ : GCCBuiltin<"__builtin_ppc_fctiwz">,
+ Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+ def int_ppc_fctudz
+ : GCCBuiltin<"__builtin_ppc_fctudz">,
+ Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
+ def int_ppc_fctuwz
+ : GCCBuiltin<"__builtin_ppc_fctuwz">,
+ Intrinsic <[llvm_double_ty], [llvm_double_ty], [IntrNoMem]>;
}
-
let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.".
/// PowerPC_Vec_Intrinsic - Base class for all altivec intrinsics.
class PowerPC_Vec_Intrinsic<string GCCIntSuffix, list<LLVMType> ret_types,
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index dc6a0c1a30e1c..aad6c5dd13b3c 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1725,3 +1725,9 @@ def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
(STDCX g8rc:$A, ForceXForm:$dst)>;
def : Pat<(int_ppc_ldarx ForceXForm:$dst),
(LDARX ForceXForm:$dst)>;
+def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, i32:$IMM),
+ (TD $IMM, $A, $B)>;
+
+// trapd
+def : Pat<(int_ppc_trapd g8rc:$A),
+ (TDI 24, $A, 0)>;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 20429ee664b21..eea5c6de4be28 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5416,3 +5416,24 @@ def : Pat<(int_ppc_lwarx ForceXForm:$dst),
(LWARX ForceXForm:$dst)>;
def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),
(STWCX gprc:$A, ForceXForm:$dst)>;
+def : Pat<(int_ppc_tw gprc:$A, gprc:$B, i32:$IMM),
+ (TW $IMM, $A, $B)>;
+def : Pat<(int_ppc_trap gprc:$A),
+ (TWI 24, $A, 0)>;
+
+def : Pat<(int_ppc_fcfid f64:$A),
+ (XSCVSXDDP $A)>;
+def : Pat<(int_ppc_fcfud f64:$A),
+ (XSCVUXDDP $A)>;
+def : Pat<(int_ppc_fctid f64:$A),
+ (FCTID $A)>;
+def : Pat<(int_ppc_fctidz f64:$A),
+ (XSCVDPSXDS $A)>;
+def : Pat<(int_ppc_fctiw f64:$A),
+ (FCTIW $A)>;
+def : Pat<(int_ppc_fctiwz f64:$A),
+ (XSCVDPSXWS $A)>;
+def : Pat<(int_ppc_fctudz f64:$A),
+ (XSCVDPUXDS $A)>;
+def : Pat<(int_ppc_fctuwz f64:$A),
+ (XSCVDPUXWS $A)>;
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
new file mode 100644
index 0000000000000..0bc1e17d5d68a
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
@@ -0,0 +1,89 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+
+declare double @llvm.ppc.fcfid(double %a)
+define dso_local double @test_fcfid(double %a) {
+; CHECK-LABEL: test_fcfid:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xscvsxddp 1, 1
+; CHECK-NEXT: blr
+ %1 = call double @llvm.ppc.fcfid(double %a)
+ ret double %1
+}
+
+declare double @llvm.ppc.fcfud(double %a)
+define dso_local double @test_fcfud(double %a) {
+; CHECK-LABEL: test_fcfud:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xscvuxddp 1, 1
+; CHECK-NEXT: blr
+ %1 = call double @llvm.ppc.fcfud(double %a)
+ ret double %1
+}
+
+declare double @llvm.ppc.fctid(double %a)
+define dso_local double @test_fctid(double %a) {
+; CHECK-LABEL: test_fctid:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fctid 1, 1
+; CHECK-NEXT: blr
+ %1 = call double @llvm.ppc.fctid(double %a)
+ ret double %1
+}
+
+declare double @llvm.ppc.fctidz(double %a)
+define dso_local double @test_fctidz(double %a) {
+; CHECK-LABEL: test_fctidz:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fctid 1, 1
+; CHECK-NEXT: blr
+ %1 = call double @llvm.ppc.fctid(double %a)
+ ret double %1
+}
+
+declare double @llvm.ppc.fctiw(double %a)
+define dso_local double @test_fctiw(double %a) {
+; CHECK-LABEL: test_fctiw:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fctid 1, 1
+; CHECK-NEXT: blr
+ %1 = call double @llvm.ppc.fctid(double %a)
+ ret double %1
+}
+
+declare double @llvm.ppc.fctiwz(double %a)
+define dso_local double @test_fctiwz(double %a) {
+; CHECK-LABEL: test_fctiwz:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fctid 1, 1
+; CHECK-NEXT: blr
+ %1 = call double @llvm.ppc.fctid(double %a)
+ ret double %1
+}
+
+declare double @llvm.ppc.fctudz(double %a)
+define dso_local double @test_fctudz(double %a) {
+; CHECK-LABEL: test_fctudz:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fctid 1, 1
+; CHECK-NEXT: blr
+ %1 = call double @llvm.ppc.fctid(double %a)
+ ret double %1
+}
+
+declare double @llvm.ppc.fctuwz(double %a)
+define dso_local double @test_fctuwz(double %a) {
+; CHECK-LABEL: test_fctuwz:
+; CHECK: # %bb.0:
+; CHECK-NEXT: fctid 1, 1
+; CHECK-NEXT: blr
+ %1 = call double @llvm.ppc.fctid(double %a)
+ ret double %1
+}
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
new file mode 100644
index 0000000000000..3afdd6f262cf0
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
@@ -0,0 +1,136 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+
+; tdw
+declare void @llvm.ppc.tdw(i64 %a, i64 %b, i32 immarg)
+define dso_local void @test__tdwlgt(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwlgt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdlgt 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 1)
+ ret void
+}
+
+define dso_local void @test__tdwllt(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwllt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdllt 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 2)
+ ret void
+}
+
+define dso_local void @test__tdw3(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdw3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: td 3, 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 3)
+ ret void
+}
+define dso_local void @test__tdweq(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdweq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdeq 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 4)
+ ret void
+}
+
+define dso_local void @test__tdwlge(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwlge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: td 5, 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 5)
+ ret void
+}
+
+define dso_local void @test__tdwlle(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwlle:
+; CHECK: # %bb.0:
+; CHECK-NEXT: td 6, 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 6)
+ ret void
+}
+
+define dso_local void @test__tdwgt(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwgt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdgt 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 8)
+ ret void
+}
+
+define dso_local void @test__tdwge(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: td 12, 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 12)
+ ret void
+}
+
+define dso_local void @test__tdwlt(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwlt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdlt 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 16)
+ ret void
+}
+
+define dso_local void @test__tdwle(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwle:
+; CHECK: # %bb.0:
+; CHECK-NEXT: td 20, 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 20)
+ ret void
+}
+
+define dso_local void @test__tdwne24(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdwne24:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdne 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 24)
+ ret void
+}
+
+define dso_local void @test__tdw31(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdw31:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdu 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 31)
+ ret void
+}
+
+define dso_local void @test__tdw_no_match(i64 %a, i64 %b) {
+; CHECK-LABEL: test__tdw_no_match:
+; CHECK: # %bb.0:
+; CHECK-NEXT: td 13, 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tdw(i64 %a, i64 %b, i32 13)
+ ret void
+}
+
+; trapd
+declare void @llvm.ppc.trapd(i64 %a)
+define dso_local void @test__trapd(i64 %a) {
+; CHECK-LABEL: test__trapd:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tdnei 3, 0
+; CHECK-NEXT: blr
+ call void @llvm.ppc.trapd(i64 %a)
+ ret void
+}
diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
new file mode 100644
index 0000000000000..406d98767f8cd
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
@@ -0,0 +1,139 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s
+
+; tw
+declare void @llvm.ppc.tw(i32 %a, i32 %b, i32 %c)
+define dso_local void @test__twlgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlgt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twlgt 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 %b, i32 1)
+ ret void
+}
+
+define dso_local void @test__twllt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twllt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twllt 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 %b, i32 2)
+ ret void
+}
+
+define dso_local void @test__tw3(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tw3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tw 3, 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 %b, i32 3)
+ ret void
+}
+
+define dso_local void @test__tweq(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tweq:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tweq 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 %b, i32 4)
+ ret void
+}
+
+define dso_local void @test__twlge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tw 5, 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 %b, i32 5)
+ ret void
+}
+
+define dso_local void @test__twlle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlle:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tw 6, 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 %b, i32 6)
+ ret void
+}
+
+define dso_local void @test__twgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twgt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twgt 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 %b, i32 8)
+ ret void
+}
+
+define dso_local void @test__twge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twge:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tw 12, 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 %b, i32 12)
+ ret void
+}
+
+define dso_local void @test__twlt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlt:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twlt 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 %b, i32 16)
+ ret void
+}
+
+define dso_local void @test__twle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twle:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tw 20, 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 %b, i32 20)
+ ret void
+}
+
+define dso_local void @test__twne24(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twne24:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twne 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 %b, i32 24)
+ ret void
+}
+
+define dso_local void @test__twu(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twu:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twu 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 %b, i32 31)
+ ret void
+}
+
+define dso_local void @test__tw_no_match(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tw_no_match:
+; CHECK: # %bb.0:
+; CHECK-NEXT: tw 13, 3, 4
+; CHECK-NEXT: blr
+ call void @llvm.ppc.tw(i32 %a, i32 %b, i32 13)
+ ret void
+}
+
+; trap
+declare void @llvm.ppc.trap(i32 %a)
+define dso_local void @test__trap(i32 %a) {
+; CHECK-LABEL: test__trap:
+; CHECK: # %bb.0:
+; CHECK-NEXT: twnei 3, 0
+; CHECK-NEXT: blr
+ call void @llvm.ppc.trap(i32 %a)
+ ret void
+}
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