[PATCH] D105800: [AMDGPU] Tidy SReg/SGPR definitions using template class

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:1242-1243
 // 96-bit bitcast
-def : BitConvert <v3i32, v3f32, SGPR_96>;
-def : BitConvert <v3f32, v3i32, SGPR_96>;
+def : BitConvert <v3i32, v3f32, SReg_96>;
+def : BitConvert <v3f32, v3i32, SReg_96>;
 
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foad wrote:
> Was SGPR_96 some kind of anomaly among the existing classes?
I think the *GPR_* class names are better where applicable


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.td:733
+    // alphanumeric ordering of their names.
+    // The superclass for inherence is the last one in topological order
+    // (i.e. enumeration order), hence SReg_ is selected over SGPR_.
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Typo inherence


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105800/new/

https://reviews.llvm.org/D105800