[PATCH] D105799: [X86] Enable half type support in inline assembly constraints

[LuoYuanke via Phabricator via llvm-commits]

LuoYuanke added inline comments.


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Comment at: llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll:22
+; CHECK-STDERR: couldn't allocate output register for constraint 'x'
+define <32 x half> @mask_Yk_f16(i8 signext %msk, <32 x half> %x, <32 x half> %y) {
+entry:
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Add more vector types (half, <8 x half>) to improve the coverage?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105799/new/

https://reviews.llvm.org/D105799