[PATCH] D105730: [SLP] match logical and/or as reduction candidates

[Alexey Bataev via Phabricator via llvm-commits]

ABataev added inline comments.


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Comment at: llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll:448
+; CHECK-NEXT:    [[CMP20:%.*]] = icmp sgt i32 [[TMP0]], 255
+; CHECK-NEXT:    [[OR_COND6:%.*]] = select i1 [[TMP10]], i1 true, i1 [[CMP20]]
+; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]]
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spatel wrote:
> spatel wrote:
> > RKSimon wrote:
> > > any idea why we only match one of the reduction chains?
> > I haven't stepped through yet. We did make some adjustments for sorting the reduction ops in previous patches, but I doubt that extended to creating multiple reductions and/or re-running analysis after forming a reduction.
> To be more specific, this test should be adapted into an SLP-only test - the enhancement will need to happen within SLP to handle mapping reduction ops into multiple reductions in some way.
Investigated it, looks like inefficiency in multi-node analysis (we're forming mixed operand nodes, like `{extract 0, extract 1, extract 2, extract 3, 0.0, 0.0, 0.0, 0.0}` and `{1.0, 1.0, 1.0, 1.0, extract 0, extract 1, extract 2, extract 3}`, which are considered as gathers). I hope this can be fixed by D101109.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105730/new/

https://reviews.llvm.org/D105730