[PATCH] D105570: [AArch64][SME] Add matrix register definitions and parsing support

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes marked 3 inline comments as done.
c-rhodes added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:2474
+      .Case("za1v.h", AArch64::ZAH1)
+      .Case("za0v.b", AArch64::ZAB0)
+      .Default(0);
----------------
CarolineConcatto wrote:
> Should za be here too?
> let SubRegIndices = [zasubb] in {
>   def ZA : AArch64Reg<0, "za", [ZAB0]>;
> }
> Should za be here too?

I think so but adding it breaks the `smstart za` instruction that aliases `MSR SVCRZA, #1`, introduced in D105576. Although having looked into it I was a bit surprised to find `za` gets parsed as a scalar register and by adding it to the switch it matches as a matrix in `matchRegisterNameAlias`, but since the kind it's matching against (scalar) doesn't match it no longer parses. It's a bit of fluke the alias gets parsed so I'll add `za` to the switch here and see if I can fix the parsing for the alias in D105576.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105570/new/

https://reviews.llvm.org/D105570