[llvm] 86109fa - [RISCV] Add test cases for div/rem with constant left hand side. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Jul 10 17:23:30 PDT 2021
Author: Craig Topper
Date: 2021-07-10T17:22:40-07:00
New Revision: 86109fa9e84cd6630f5f14414779b890144b3fc3
URL: https://github.com/llvm/llvm-project/commit/86109fa9e84cd6630f5f14414779b890144b3fc3
DIFF: https://github.com/llvm/llvm-project/commit/86109fa9e84cd6630f5f14414779b890144b3fc3.diff
LOG: [RISCV] Add test cases for div/rem with constant left hand side. NFC
Some of these would produce better code if we used W instructions,
but constant LHS currently prevents that.
Added:
Modified:
llvm/test/CodeGen/RISCV/div.ll
llvm/test/CodeGen/RISCV/rem.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/div.ll b/llvm/test/CodeGen/RISCV/div.ll
index a7db30213cc30..8bfc66e7a82a3 100644
--- a/llvm/test/CodeGen/RISCV/div.ll
+++ b/llvm/test/CodeGen/RISCV/div.ll
@@ -114,6 +114,47 @@ define i32 @udiv_pow2(i32 %a) nounwind {
ret i32 %1
}
+define i32 @udiv_constant_lhs(i32 %a) nounwind {
+; RV32I-LABEL: udiv_constant_lhs:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: addi a0, zero, 10
+; RV32I-NEXT: call __udivsi3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IM-LABEL: udiv_constant_lhs:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: addi a1, zero, 10
+; RV32IM-NEXT: divu a0, a1, a0
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: udiv_constant_lhs:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, a0, 32
+; RV64I-NEXT: srli a1, a0, 32
+; RV64I-NEXT: addi a0, zero, 10
+; RV64I-NEXT: call __udivdi3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: udiv_constant_lhs:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: slli a0, a0, 32
+; RV64IM-NEXT: srli a0, a0, 32
+; RV64IM-NEXT: addi a1, zero, 10
+; RV64IM-NEXT: divu a0, a1, a0
+; RV64IM-NEXT: ret
+ %1 = udiv i32 10, %a
+ ret i32 %1
+}
+
define i64 @udiv64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: udiv64:
; RV32I: # %bb.0:
@@ -200,6 +241,53 @@ define i64 @udiv64_constant(i64 %a) nounwind {
ret i64 %1
}
+define i64 @udiv64_constant_lhs(i64 %a) nounwind {
+; RV32I-LABEL: udiv64_constant_lhs:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv a3, a1
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: addi a0, zero, 10
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __udivdi3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IM-LABEL: udiv64_constant_lhs:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: addi sp, sp, -16
+; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IM-NEXT: mv a3, a1
+; RV32IM-NEXT: mv a2, a0
+; RV32IM-NEXT: addi a0, zero, 10
+; RV32IM-NEXT: mv a1, zero
+; RV32IM-NEXT: call __udivdi3 at plt
+; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IM-NEXT: addi sp, sp, 16
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: udiv64_constant_lhs:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: addi a0, zero, 10
+; RV64I-NEXT: call __udivdi3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: udiv64_constant_lhs:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: addi a1, zero, 10
+; RV64IM-NEXT: divu a0, a1, a0
+; RV64IM-NEXT: ret
+ %1 = udiv i64 10, %a
+ ret i64 %1
+}
+
define i8 @udiv8(i8 %a, i8 %b) nounwind {
; RV32I-LABEL: udiv8:
; RV32I: # %bb.0:
@@ -310,6 +398,46 @@ define i8 @udiv8_pow2(i8 %a) nounwind {
ret i8 %1
}
+define i8 @udiv8_constant_lhs(i8 %a) nounwind {
+; RV32I-LABEL: udiv8_constant_lhs:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a1, a0, 255
+; RV32I-NEXT: addi a0, zero, 10
+; RV32I-NEXT: call __udivsi3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IM-LABEL: udiv8_constant_lhs:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: andi a0, a0, 255
+; RV32IM-NEXT: addi a1, zero, 10
+; RV32IM-NEXT: divu a0, a1, a0
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: udiv8_constant_lhs:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a1, a0, 255
+; RV64I-NEXT: addi a0, zero, 10
+; RV64I-NEXT: call __udivdi3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: udiv8_constant_lhs:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: andi a0, a0, 255
+; RV64IM-NEXT: addi a1, zero, 10
+; RV64IM-NEXT: divu a0, a1, a0
+; RV64IM-NEXT: ret
+ %1 = udiv i8 10, %a
+ ret i8 %1
+}
+
define i16 @udiv16(i16 %a, i16 %b) nounwind {
; RV32I-LABEL: udiv16:
; RV32I: # %bb.0:
@@ -438,6 +566,54 @@ define i16 @udiv16_pow2(i16 %a) nounwind {
ret i16 %1
}
+define i16 @udiv16_constant_lhs(i16 %a) nounwind {
+; RV32I-LABEL: udiv16_constant_lhs:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a1, a0, a1
+; RV32I-NEXT: addi a0, zero, 10
+; RV32I-NEXT: call __udivsi3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IM-LABEL: udiv16_constant_lhs:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: lui a1, 16
+; RV32IM-NEXT: addi a1, a1, -1
+; RV32IM-NEXT: and a0, a0, a1
+; RV32IM-NEXT: addi a1, zero, 10
+; RV32IM-NEXT: divu a0, a1, a0
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: udiv16_constant_lhs:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a1, a0, a1
+; RV64I-NEXT: addi a0, zero, 10
+; RV64I-NEXT: call __udivdi3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: udiv16_constant_lhs:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: lui a1, 16
+; RV64IM-NEXT: addiw a1, a1, -1
+; RV64IM-NEXT: and a0, a0, a1
+; RV64IM-NEXT: addi a1, zero, 10
+; RV64IM-NEXT: divu a0, a1, a0
+; RV64IM-NEXT: ret
+ %1 = udiv i16 10, %a
+ ret i16 %1
+}
+
define i32 @sdiv(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sdiv:
; RV32I: # %bb.0:
@@ -556,6 +732,45 @@ define i32 @sdiv_pow2(i32 %a) nounwind {
ret i32 %1
}
+define i32 @sdiv_constant_lhs(i32 %a) nounwind {
+; RV32I-LABEL: sdiv_constant_lhs:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: addi a0, zero, -10
+; RV32I-NEXT: call __divsi3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IM-LABEL: sdiv_constant_lhs:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: addi a1, zero, -10
+; RV32IM-NEXT: div a0, a1, a0
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: sdiv_constant_lhs:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sext.w a1, a0
+; RV64I-NEXT: addi a0, zero, -10
+; RV64I-NEXT: call __divdi3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: sdiv_constant_lhs:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: sext.w a0, a0
+; RV64IM-NEXT: addi a1, zero, -10
+; RV64IM-NEXT: div a0, a1, a0
+; RV64IM-NEXT: ret
+ %1 = sdiv i32 -10, %a
+ ret i32 %1
+}
+
define i64 @sdiv64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: sdiv64:
; RV32I: # %bb.0:
@@ -644,6 +859,53 @@ define i64 @sdiv64_constant(i64 %a) nounwind {
ret i64 %1
}
+define i64 @sdiv64_constant_lhs(i64 %a) nounwind {
+; RV32I-LABEL: sdiv64_constant_lhs:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv a3, a1
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: addi a0, zero, 10
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __divdi3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IM-LABEL: sdiv64_constant_lhs:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: addi sp, sp, -16
+; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IM-NEXT: mv a3, a1
+; RV32IM-NEXT: mv a2, a0
+; RV32IM-NEXT: addi a0, zero, 10
+; RV32IM-NEXT: mv a1, zero
+; RV32IM-NEXT: call __divdi3 at plt
+; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IM-NEXT: addi sp, sp, 16
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: sdiv64_constant_lhs:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: addi a0, zero, 10
+; RV64I-NEXT: call __divdi3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: sdiv64_constant_lhs:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: addi a1, zero, 10
+; RV64IM-NEXT: div a0, a1, a0
+; RV64IM-NEXT: ret
+ %1 = sdiv i64 10, %a
+ ret i64 %1
+}
+
; Although this sdiv has two sexti32 operands, it shouldn't compile to divw on
; RV64M as that wouldn't produce the correct result for e.g. INT_MIN/-1.
@@ -843,6 +1105,50 @@ define i8 @sdiv8_pow2(i8 %a) nounwind {
ret i8 %1
}
+define i8 @sdiv8_constant_lhs(i8 %a) nounwind {
+; RV32I-LABEL: sdiv8_constant_lhs:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a0, a0, 24
+; RV32I-NEXT: srai a1, a0, 24
+; RV32I-NEXT: addi a0, zero, -10
+; RV32I-NEXT: call __divsi3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IM-LABEL: sdiv8_constant_lhs:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: slli a0, a0, 24
+; RV32IM-NEXT: srai a0, a0, 24
+; RV32IM-NEXT: addi a1, zero, -10
+; RV32IM-NEXT: div a0, a1, a0
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: sdiv8_constant_lhs:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, a0, 56
+; RV64I-NEXT: srai a1, a0, 56
+; RV64I-NEXT: addi a0, zero, -10
+; RV64I-NEXT: call __divdi3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: sdiv8_constant_lhs:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: slli a0, a0, 56
+; RV64IM-NEXT: srai a0, a0, 56
+; RV64IM-NEXT: addi a1, zero, -10
+; RV64IM-NEXT: div a0, a1, a0
+; RV64IM-NEXT: ret
+ %1 = sdiv i8 -10, %a
+ ret i8 %1
+}
+
define i16 @sdiv16(i16 %a, i16 %b) nounwind {
; RV32I-LABEL: sdiv16:
; RV32I: # %bb.0:
@@ -991,3 +1297,47 @@ define i16 @sdiv16_pow2(i16 %a) nounwind {
%1 = sdiv i16 %a, 8
ret i16 %1
}
+
+define i16 @sdiv16_constant_lhs(i16 %a) nounwind {
+; RV32I-LABEL: sdiv16_constant_lhs:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a0, a0, 16
+; RV32I-NEXT: srai a1, a0, 16
+; RV32I-NEXT: addi a0, zero, -10
+; RV32I-NEXT: call __divsi3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IM-LABEL: sdiv16_constant_lhs:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: slli a0, a0, 16
+; RV32IM-NEXT: srai a0, a0, 16
+; RV32IM-NEXT: addi a1, zero, -10
+; RV32IM-NEXT: div a0, a1, a0
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: sdiv16_constant_lhs:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, a0, 48
+; RV64I-NEXT: srai a1, a0, 48
+; RV64I-NEXT: addi a0, zero, -10
+; RV64I-NEXT: call __divdi3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: sdiv16_constant_lhs:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: slli a0, a0, 48
+; RV64IM-NEXT: srai a0, a0, 48
+; RV64IM-NEXT: addi a1, zero, -10
+; RV64IM-NEXT: div a0, a1, a0
+; RV64IM-NEXT: ret
+ %1 = sdiv i16 -10, %a
+ ret i16 %1
+}
diff --git a/llvm/test/CodeGen/RISCV/rem.ll b/llvm/test/CodeGen/RISCV/rem.ll
index 246b2394c74e8..bda53ce9731de 100644
--- a/llvm/test/CodeGen/RISCV/rem.ll
+++ b/llvm/test/CodeGen/RISCV/rem.ll
@@ -44,11 +44,54 @@ define i32 @urem(i32 %a, i32 %b) nounwind {
ret i32 %1
}
-define i32 @srem(i32 %a, i32 %b) nounwind {
+define i32 @urem_constant_lhs(i32 %a) nounwind {
+; RV32I-LABEL: urem_constant_lhs:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: addi a0, zero, 10
+; RV32I-NEXT: call __umodsi3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IM-LABEL: urem_constant_lhs:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: addi a1, zero, 10
+; RV32IM-NEXT: remu a0, a1, a0
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: urem_constant_lhs:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, a0, 32
+; RV64I-NEXT: srli a1, a0, 32
+; RV64I-NEXT: addi a0, zero, 10
+; RV64I-NEXT: call __umoddi3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: urem_constant_lhs:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: slli a0, a0, 32
+; RV64IM-NEXT: srli a0, a0, 32
+; RV64IM-NEXT: addi a1, zero, 10
+; RV64IM-NEXT: remu a0, a1, a0
+; RV64IM-NEXT: ret
+ %1 = urem i32 10, %a
+ ret i32 %1
+}
+
+define i32 @srem(i32 %a) nounwind {
; RV32I-LABEL: srem:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv a1, a0
+; RV32I-NEXT: addi a0, zero, -10
; RV32I-NEXT: call __modsi3 at plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
@@ -56,15 +99,16 @@ define i32 @srem(i32 %a, i32 %b) nounwind {
;
; RV32IM-LABEL: srem:
; RV32IM: # %bb.0:
-; RV32IM-NEXT: rem a0, a0, a1
+; RV32IM-NEXT: addi a1, zero, -10
+; RV32IM-NEXT: rem a0, a1, a0
; RV32IM-NEXT: ret
;
; RV64I-LABEL: srem:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sext.w a0, a0
-; RV64I-NEXT: sext.w a1, a1
+; RV64I-NEXT: sext.w a1, a0
+; RV64I-NEXT: addi a0, zero, -10
; RV64I-NEXT: call __moddi3 at plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
@@ -72,9 +116,10 @@ define i32 @srem(i32 %a, i32 %b) nounwind {
;
; RV64IM-LABEL: srem:
; RV64IM: # %bb.0:
-; RV64IM-NEXT: remw a0, a0, a1
+; RV64IM-NEXT: addi a1, zero, -10
+; RV64IM-NEXT: remw a0, a1, a0
; RV64IM-NEXT: ret
- %1 = srem i32 %a, %b
+ %1 = srem i32 -10, %a
ret i32 %1
}
@@ -114,6 +159,53 @@ define i64 @urem64(i64 %a, i64 %b) nounwind {
ret i64 %1
}
+define i64 @urem64_constant_lhs(i64 %a) nounwind {
+; RV32I-LABEL: urem64_constant_lhs:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv a3, a1
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: addi a0, zero, 10
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: call __umoddi3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IM-LABEL: urem64_constant_lhs:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: addi sp, sp, -16
+; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IM-NEXT: mv a3, a1
+; RV32IM-NEXT: mv a2, a0
+; RV32IM-NEXT: addi a0, zero, 10
+; RV32IM-NEXT: mv a1, zero
+; RV32IM-NEXT: call __umoddi3 at plt
+; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IM-NEXT: addi sp, sp, 16
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: urem64_constant_lhs:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: addi a0, zero, 10
+; RV64I-NEXT: call __umoddi3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: urem64_constant_lhs:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: addi a1, zero, 10
+; RV64IM-NEXT: remu a0, a1, a0
+; RV64IM-NEXT: ret
+ %1 = urem i64 10, %a
+ ret i64 %1
+}
+
define i64 @srem64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: srem64:
; RV32I: # %bb.0:
@@ -150,6 +242,53 @@ define i64 @srem64(i64 %a, i64 %b) nounwind {
ret i64 %1
}
+define i64 @srem64_constant_lhs(i64 %a) nounwind {
+; RV32I-LABEL: srem64_constant_lhs:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv a3, a1
+; RV32I-NEXT: mv a2, a0
+; RV32I-NEXT: addi a0, zero, -10
+; RV32I-NEXT: addi a1, zero, -1
+; RV32I-NEXT: call __moddi3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IM-LABEL: srem64_constant_lhs:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: addi sp, sp, -16
+; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IM-NEXT: mv a3, a1
+; RV32IM-NEXT: mv a2, a0
+; RV32IM-NEXT: addi a0, zero, -10
+; RV32IM-NEXT: addi a1, zero, -1
+; RV32IM-NEXT: call __moddi3 at plt
+; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IM-NEXT: addi sp, sp, 16
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: srem64_constant_lhs:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: addi a0, zero, -10
+; RV64I-NEXT: call __moddi3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: srem64_constant_lhs:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: addi a1, zero, -10
+; RV64IM-NEXT: rem a0, a1, a0
+; RV64IM-NEXT: ret
+ %1 = srem i64 -10, %a
+ ret i64 %1
+}
+
define i8 @urem8(i8 %a, i8 %b) nounwind {
; RV32I-LABEL: urem8:
; RV32I: # %bb.0:
@@ -190,6 +329,47 @@ define i8 @urem8(i8 %a, i8 %b) nounwind {
ret i8 %1
}
+define i8 @urem8_constant_lhs(i8 %a) nounwind {
+; RV32I-LABEL: urem8_constant_lhs:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: andi a1, a0, 255
+; RV32I-NEXT: addi a0, zero, 10
+; RV32I-NEXT: call __umodsi3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IM-LABEL: urem8_constant_lhs:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: andi a0, a0, 255
+; RV32IM-NEXT: addi a1, zero, 10
+; RV32IM-NEXT: remu a0, a1, a0
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: urem8_constant_lhs:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: andi a1, a0, 255
+; RV64I-NEXT: addi a0, zero, 10
+; RV64I-NEXT: call __umoddi3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: urem8_constant_lhs:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: andi a0, a0, 255
+; RV64IM-NEXT: addi a1, zero, 10
+; RV64IM-NEXT: remu a0, a1, a0
+; RV64IM-NEXT: ret
+ %1 = urem i8 10, %a
+ ret i8 %1
+}
+
+
define i8 @srem8(i8 %a, i8 %b) nounwind {
; RV32I-LABEL: srem8:
; RV32I: # %bb.0:
@@ -238,6 +418,51 @@ define i8 @srem8(i8 %a, i8 %b) nounwind {
ret i8 %1
}
+define i8 @srem8_constant_lhs(i8 %a) nounwind {
+; RV32I-LABEL: srem8_constant_lhs:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a0, a0, 24
+; RV32I-NEXT: srai a1, a0, 24
+; RV32I-NEXT: addi a0, zero, -10
+; RV32I-NEXT: call __modsi3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IM-LABEL: srem8_constant_lhs:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: slli a0, a0, 24
+; RV32IM-NEXT: srai a0, a0, 24
+; RV32IM-NEXT: addi a1, zero, -10
+; RV32IM-NEXT: rem a0, a1, a0
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: srem8_constant_lhs:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, a0, 56
+; RV64I-NEXT: srai a1, a0, 56
+; RV64I-NEXT: addi a0, zero, -10
+; RV64I-NEXT: call __moddi3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: srem8_constant_lhs:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: slli a0, a0, 56
+; RV64IM-NEXT: srai a0, a0, 56
+; RV64IM-NEXT: addi a1, zero, -10
+; RV64IM-NEXT: remw a0, a1, a0
+; RV64IM-NEXT: ret
+ %1 = srem i8 -10, %a
+ ret i8 %1
+}
+
+
define i16 @urem16(i16 %a, i16 %b) nounwind {
; RV32I-LABEL: urem16:
; RV32I: # %bb.0:
@@ -286,6 +511,54 @@ define i16 @urem16(i16 %a, i16 %b) nounwind {
ret i16 %1
}
+define i16 @urem16_constant_lhs(i16 %a) nounwind {
+; RV32I-LABEL: urem16_constant_lhs:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -1
+; RV32I-NEXT: and a1, a0, a1
+; RV32I-NEXT: addi a0, zero, 10
+; RV32I-NEXT: call __umodsi3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IM-LABEL: urem16_constant_lhs:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: lui a1, 16
+; RV32IM-NEXT: addi a1, a1, -1
+; RV32IM-NEXT: and a0, a0, a1
+; RV32IM-NEXT: addi a1, zero, 10
+; RV32IM-NEXT: remu a0, a1, a0
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: urem16_constant_lhs:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: lui a1, 16
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: and a1, a0, a1
+; RV64I-NEXT: addi a0, zero, 10
+; RV64I-NEXT: call __umoddi3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: urem16_constant_lhs:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: lui a1, 16
+; RV64IM-NEXT: addiw a1, a1, -1
+; RV64IM-NEXT: and a0, a0, a1
+; RV64IM-NEXT: addi a1, zero, 10
+; RV64IM-NEXT: remu a0, a1, a0
+; RV64IM-NEXT: ret
+ %1 = urem i16 10, %a
+ ret i16 %1
+}
+
define i16 @srem16(i16 %a, i16 %b) nounwind {
; RV32I-LABEL: srem16:
; RV32I: # %bb.0:
@@ -333,3 +606,47 @@ define i16 @srem16(i16 %a, i16 %b) nounwind {
%1 = srem i16 %a, %b
ret i16 %1
}
+
+define i16 @srem16_constant_lhs(i16 %a) nounwind {
+; RV32I-LABEL: srem16_constant_lhs:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: slli a0, a0, 16
+; RV32I-NEXT: srai a1, a0, 16
+; RV32I-NEXT: addi a0, zero, -10
+; RV32I-NEXT: call __modsi3 at plt
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
+; RV32I-NEXT: ret
+;
+; RV32IM-LABEL: srem16_constant_lhs:
+; RV32IM: # %bb.0:
+; RV32IM-NEXT: slli a0, a0, 16
+; RV32IM-NEXT: srai a0, a0, 16
+; RV32IM-NEXT: addi a1, zero, -10
+; RV32IM-NEXT: rem a0, a1, a0
+; RV32IM-NEXT: ret
+;
+; RV64I-LABEL: srem16_constant_lhs:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: slli a0, a0, 48
+; RV64I-NEXT: srai a1, a0, 48
+; RV64I-NEXT: addi a0, zero, -10
+; RV64I-NEXT: call __moddi3 at plt
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
+; RV64I-NEXT: ret
+;
+; RV64IM-LABEL: srem16_constant_lhs:
+; RV64IM: # %bb.0:
+; RV64IM-NEXT: slli a0, a0, 48
+; RV64IM-NEXT: srai a0, a0, 48
+; RV64IM-NEXT: addi a1, zero, -10
+; RV64IM-NEXT: remw a0, a1, a0
+; RV64IM-NEXT: ret
+ %1 = srem i16 -10, %a
+ ret i16 %1
+}
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