[PATCH] D105730: [SLP] match logical and/or as reduction candidates

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll:13
+; CHECK-NEXT:    [[TMP2:%.*]] = bitcast <4 x i1> [[TMP1]] to i4
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq i4 [[TMP2]], -1
+; CHECK-NEXT:    br i1 [[TMP3]], label [[COMMON_RET:%.*]], label [[LOR_LHS_FALSE:%.*]]
----------------
It doesn't have to be part of this - but should we be trying to fold these patterns to a reduction intrinsic ?

```
; CHECK-NEXT:    [[TMP0:%.*]] = fcmp olt <4 x float> [[T:%.*]], zeroinitializer
; CHECK-NEXT:    [[TMP1:%.*]] = freeze <4 x i1> [[TMP0]]
; CHECK-NEXT:    [[TMP3:%.*]] = call i1 llvm.vector.reduce.and.v4i1([[TMP1]])
```


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105730/new/

https://reviews.llvm.org/D105730