[PATCH] D105676: [AArch64][GlobalISel] Relax oneuse restriction for PTR_ADD chain combining to check addressing legality.

[Sebastian Neubauer via Phabricator via llvm-commits]

sebastian-ne added a comment.

> does this fix your internal regression?

Yes, thanks a lot.
FWIW, the “internal regression” is D103326 <https://reviews.llvm.org/D103326>, all the test changes there were gone after I rebased it upon D105069 <https://reviews.llvm.org/D105069>.

There is now only a single case, where slightly worse code than is generated compared to before D105069 <https://reviews.llvm.org/D105069>: https://github.com/llvm/llvm-project/blob/c282d55a38577e076b48cd7a8113e5eb0a2039cd/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll#L4151-L4164
`isLegalAddressingMode` correctly returns false and the dead loads from the <64 x i32> load (which are multiple users of the G_PTR_ADD) are only removed later, after the G_PTR_ADD has long been converted to pseudo instructions. I guess there’s not much we can do about that.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105676/new/

https://reviews.llvm.org/D105676