[PATCH] D105570: [AArch64][SME] Add matrix register definitions and parsing support

[Caroline via Phabricator via llvm-commits]

CarolineConcatto added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64RegisterInfo.td:1182
+def ZAQ8 : AArch64Reg<8, "za8.q">;
+def ZAQ9 : AArch64Reg<9, "za9.q">;
+def ZAQ10 : AArch64Reg<10, "za10.q">;
----------------
Should it be all aligned?


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Comment at: llvm/lib/Target/AArch64/AArch64RegisterInfo.td:1321
+  let DecoderMethod = "DecodeMatrixTile<" # NumBitsForTile # ">";
+  let PrintMethod   = "printMatrixTileVector<" # IsVertical # ">";
+}
----------------
nit: remove extra space



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Comment at: llvm/lib/Target/AArch64/AArch64RegisterInfo.td:1324
+
+def TileVectorOpH8   : MatrixTileVectorOperand<  8, 0, MPR8, 0>;
+def TileVectorOpH16  : MatrixTileVectorOperand< 16, 1, MPR16, 0>;
----------------
nit: Should you align all elements?
The last ones are not.


================
Comment at: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:2474
+      .Case("za1v.h", AArch64::ZAH1)
+      .Case("za0v.b", AArch64::ZAB0)
+      .Default(0);
----------------
Should za be here too?
let SubRegIndices = [zasubb] in {
  def ZA : AArch64Reg<0, "za", [ZAB0]>;
}


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105570/new/

https://reviews.llvm.org/D105570