[PATCH] D101455: [ELF] Implement RISCV::getImplicitAddend()

[Alexander Richardson via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG97fe63753938: [ELF] Implement RISCV::getImplicitAddend() (authored by arichardson).

Changed prior to commit:
  https://reviews.llvm.org/D101455?vs=341185&id=357457#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D101455/new/

https://reviews.llvm.org/D101455

Files:
  lld/ELF/Arch/RISCV.cpp
  lld/ELF/Driver.cpp


Index: lld/ELF/Driver.cpp
===================================================================
--- lld/ELF/Driver.cpp
+++ lld/ELF/Driver.cpp
@@ -1400,8 +1400,8 @@
   // enable the debug checks for all targets, but currently not all targets
   // have support for reading Elf_Rel addends, so we only enable for a subset.
 #ifndef NDEBUG
-  bool checkDynamicRelocsDefault =
-      m == EM_ARM || m == EM_386 || m == EM_MIPS || m == EM_X86_64;
+  bool checkDynamicRelocsDefault = m == EM_ARM || m == EM_386 || m == EM_MIPS ||
+                                   m == EM_X86_64 || m == EM_RISCV;
 #else
   bool checkDynamicRelocsDefault = false;
 #endif
Index: lld/ELF/Arch/RISCV.cpp
===================================================================
--- lld/ELF/Arch/RISCV.cpp
+++ lld/ELF/Arch/RISCV.cpp
@@ -24,6 +24,7 @@
 public:
   RISCV();
   uint32_t calcEFlags() const override;
+  int64_t getImplicitAddend(const uint8_t *buf, RelType type) const override;
   void writeGotHeader(uint8_t *buf) const override;
   void writeGotPlt(uint8_t *buf, const Symbol &s) const override;
   void writeIgotPlt(uint8_t *buf, const Symbol &s) const override;
@@ -134,6 +135,28 @@
   return target;
 }
 
+int64_t RISCV::getImplicitAddend(const uint8_t *buf, RelType type) const {
+  switch (type) {
+  default:
+    internalLinkerError(getErrorLocation(buf),
+                        "cannot read addend for relocation " + toString(type));
+    return 0;
+  case R_RISCV_32:
+  case R_RISCV_TLS_DTPMOD32:
+  case R_RISCV_TLS_DTPREL32:
+    return SignExtend64<32>(read32le(buf));
+  case R_RISCV_64:
+    return read64le(buf);
+  case R_RISCV_RELATIVE:
+  case R_RISCV_IRELATIVE:
+    return config->is64 ? read64le(buf) : read32le(buf);
+  case R_RISCV_NONE:
+  case R_RISCV_JUMP_SLOT:
+    // These relocations are defined as not having an implicit addend.
+    return 0;
+  }
+}
+
 void RISCV::writeGotHeader(uint8_t *buf) const {
   if (config->is64)
     write64le(buf, mainPart->dynamic->getVA());


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