[PATCH] D105680: [ARM] Lower v16i8 -> i64 VMLA reductions.

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added inline comments.


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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:16051
   auto Create64bitNode = [&](unsigned Opcode, ArrayRef<SDValue> Ops) {
+    // Split illegal MVT::v16i8->i64 vector reductions into two legal v8i16->i64
+    // reductions. The operands are extended with MVEEXT, but as they are
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Perhaps a silly question on the use of 'illegal'. Type `v16i8` isn't an illegal type, it is just not supported for these VMLALV instructions. Thus, I was wondering if 'unsupported' would be better, to avoid possible confusion with type legalization in general if that makes sense?


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  https://reviews.llvm.org/D105680/new/

https://reviews.llvm.org/D105680