[llvm] 55bd12d - [PowerPC] Remove implicit use register after transformToImmFormFedByLI()

[Kai Luo via llvm-commits]

Author: Kai Luo
Date: 2021-07-09T04:42:54Z
New Revision: 55bd12d4b7eeed5d2909de4babaead12396c521c

URL: https://github.com/llvm/llvm-project/commit/55bd12d4b7eeed5d2909de4babaead12396c521c
DIFF: https://github.com/llvm/llvm-project/commit/55bd12d4b7eeed5d2909de4babaead12396c521c.diff

LOG: [PowerPC] Remove implicit use register after transformToImmFormFedByLI()

When the instruction has imm form and fed by LI, we can remove the redundat LI instruction.
Below is an example:
```
    renamable $x5 = LI8 2
    renamable $x4 = exact SRD killed renamable $x4, killed renamable $r5, implicit $x5
```

will be converted to:
```
   renamable $x5 = LI8 2
   renamable $x4 = exact RLDICL killed renamable $x4, 62, 2,  implicit killed $x5
```

But when we do this optimization, we forget to remove implicit killed $x5
This bug has caused a lnt case error. This patch is to fix above bug.

Reviewed By: #powerpc, shchenz

Differential Revision: https://reviews.llvm.org/D85288

Added: 
    llvm/test/CodeGen/PowerPC/remove-redundant-li-implicit-reg.mir

Modified: 
    llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
index 625730eec8213..9dd35d5f44d1a 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -3160,11 +3160,11 @@ void PPCInstrInfo::replaceInstrOperandWithImm(MachineInstr &MI,
   Register InUseReg = MI.getOperand(OpNo).getReg();
   MI.getOperand(OpNo).ChangeToImmediate(Imm);
 
-  if (MI.implicit_operands().empty())
-    return;
-
   // We need to make sure that the MI didn't have any implicit use
-  // of this REG any more.
+  // of this REG any more. We don't call MI.implicit_operands().empty() to
+  // return early, since MI's MCID might be changed in calling context, as a
+  // result its number of explicit operands may be changed, thus the begin of
+  // implicit operand is changed.
   const TargetRegisterInfo *TRI = &getRegisterInfo();
   int UseOpIdx = MI.findRegisterUseOperandIdx(InUseReg, false, TRI);
   if (UseOpIdx >= 0) {

diff  --git a/llvm/test/CodeGen/PowerPC/remove-redundant-li-implicit-reg.mir b/llvm/test/CodeGen/PowerPC/remove-redundant-li-implicit-reg.mir
new file mode 100644
index 0000000000000..90acaa8780ff6
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/remove-redundant-li-implicit-reg.mir
@@ -0,0 +1,22 @@
+# RUN: llc -mtriple=powerpc64-unknown-unknown -stop-after ppc-pre-emit-peephole \
+# RUN:   %s -o - -verify-machineinstrs | FileCheck %s
+
+---
+name: testRedundantLiImplicitReg
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3, $x4, $x5
+
+    STW killed $r3, killed $x5, 100
+    renamable $x5 = LI8 2
+    renamable $x4 = exact SRD killed renamable $x4, killed renamable $r5, implicit $x5
+    STD $x4, $x4, 100
+    BLR8 implicit $lr8, implicit $rm
+
+  ; CHECK-LABEL: testRedundantLiImplicitReg
+  ; CHECK: bb.0.entry:
+  ; CHECK:   STW killed $r3, killed $x5, 100
+  ; CHECK:   renamable $x4 = exact RLDICL killed renamable $x4, 62, 2
+  ; CHECK:   STD killed $x4, $x4, 100
+  ; CHECK:   BLR8 implicit $lr8, implicit $rm