[PATCH] D105633: [WIP] Improve code generation for vector_splice

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

Hi @CarolineConcatto,

- For a splice with a positive index, we can use the EXT instruction (if the index fits the immediate range). Because EXT operates on i8 element types, you'll need to take into account the scaling. You can use a `ComplexPattern` to test if the immediate is in range and then have it scaled, see for example `sve_cnt_mul_imm` which uses `SelectCntImm` to check whether the immediate is in range, and then scales the value.
- For a splice with a negative index, rather than using a REV you could generate a predicate that is: `0, 1, 1, ... 1` using `(not(whilelt XZR, -index))`.

The most important cases to optimize are: -1 and +1, as those will occur most in practice. In our downstream compiler, we use WHILE+LASTB+INSR instead of SPLICE for the -1 case (which I now realise may save the one `not` instruction I mention above).



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7401
+                                                  SelectionDAG &DAG) const {
+  return Op;
+}
----------------
If all we do is return `Op`, then you can just as well say it's Legal. However, in my other comment I'm suggesting to do custom-lowering to bitcast the types, so that we don't need as many patterns.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:1242
+            (LASTB_VPZ_D (PTRUE_D 31), ZPR:$Z1), dsub))>;
+  def : Pat<(nxv8f16 (vector_splice (nxv8f16 ZPR:$Z1), (nxv8f16 ZPR:$Z2), (i64 1))),
+            (INSR_ZV_H ZPR:$Z2, (INSERT_SUBREG (IMPLICIT_DEF),
----------------
The type isn't actually relevant for splice, although the container width is. If we can lower the splice operation to always work on integer types (converting the input fp vector, and a casting the result back to the original fp type afterwards), then we don't need patterns for all these cases.


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