[PATCH] D105633: [SVE][AArch64] Improve code generation for vector_splice

[Caroline via Phabricator via llvm-commits]

CarolineConcatto created this revision.
Herald added subscribers: psnobl, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
CarolineConcatto requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

This patch implements vector_splice in tablegen for:

  a) when the immediate is equal to 1 (Imm==1) and uses:
       INSR  +  LASTB + REV

For instance :
@llvm.experimental.vector.splice(Vector_1, Vector_2, 1)
@llvm.experimental.vector.splice(<A,B,C,D>, <E,F,G,H>, 1) ==> <B, C, D, E>

    REV    RevVec2, Vector_2              // RevVec2 = H, G, F, E
    LAST   RegLast, RevVec2               // RegLast = E
    INSR   Res, (vector_1 << 1), RegLast  // Res =  B, C, D +  E
                                          // Res = B, C, D, E
  
  b) for all the others cases uses:
       SPLICE + WHILE + REV

For instance :
@llvm.experimental.vector.splice(Vector_1, Vector_2, Imm)
@llvm.experimental.vector.splice(<A,B,C,D>, <E,F,G,H>, 3) ==> <D, E, F, G>

  REV    RevVec2, Vector_2                   // RevVec2 = H, G, F, E
  WHILE  Mask, zero, Imm                     // Mask = 3
  SPLICE Res , Mask, Vector_1, RevVec2       // Vector_1 = D + RevVec2 = G, F, E
                                             // Res = G, F, E, D
  REV    Res                                 // G, F, E, D ==> D, E, F, G

Not so correct when middle of the vector
@llvm.experimental.vector.splice(Vector_1, Vector_2, Imm)
@llvm.experimental.vector.splice(<A,B,C,D>, <E,F,G,H>, 2) ==> <C, D, E, F>

  REV    RevVec2, Vector_2                   // RevVec2 = H, G, F, E
  WHILE  Mask, zero, Imm                     // Mask = 2
  SPLICE Res , Mask, Vector_1, RevVec2=      // Vector_1 = C, D + RevVec2 = F, E
                                             // Res = F, E, C, D
  REV    Res                                 // F, E, C, D ==> D, C, E, F
                                             // But should be  C, D, E, F

Splice starts from the lowest active element of each vector to the last(higher) active.
And adds its part to the result vector starting from the lowest position.
So maybe vector.splice would be better if:
@llvm.experimental.vector.splice(<A,B,C,D>, <E,F,G,H>, 2) ==> <G, H, C, D>
or
@llvm.experimental.vector.splice(<A,B,C,D>, <E,F,G,H>, 2) ==> <C, D, G, H >


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D105633

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D105633.357221.patch
Type: text/x-patch
Size: 67676 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210708/1254a310/attachment-0001.bin>