[PATCH] D88663: [AArch64] Use TargetRegisterClass::hasSubClassEq in tryToFindRegisterToRename

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes added a comment.

I know this patch has stalled but it would be good to revive the discussion in the context of D105572 <https://reviews.llvm.org/D105572>, which adds MC layer support for load/store instructions in the Arm Scalable Matrix Extension (SME). These instructions (e.g. [1]) have a 32-bit slice index register in the range `W12-W15` that's defined as:

  def MatrixIndexGPR32_12_15 : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 12, 15)>;
  def MatrixIndexGPR32Op12_15 : RegisterOperand<MatrixIndexGPR32_12_15> {
    let EncoderMethod = "EncodeMatrixIndexGPR32";
  }

Adding this class is affecting the ld/st optimizer and causing differences in the tests listed here. For now I've just re-generated the tests in D105572 <https://reviews.llvm.org/D105572> but it would be good if this issue can be resolved.

[1] https://developer.arm.com/documentation/ddi0602/2021-06/SME-Instructions/LD1B--Contiguous-load-of-bytes-to-8-bit-element-ZA-tile-slice-


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https://reviews.llvm.org/D88663