[PATCH] D105596: [PowerPC] Custom Lowering BUILD_VECTOR for v2i64 for P7 as well

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf added a comment.

Code change looks fine



================
Comment at: llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll:15
 define double @caller() {
-; MIR32-LABEL: name: caller
-; MIR32: bb.0.entry:
-; MIR32:   renamable $r3 = LWZtoc @__const.caller.t, $r2 :: (load (s32) from got)
-; MIR32:   renamable $r4 = LI 31
-; MIR32:   renamable $v2 = LVX renamable $r3, killed renamable $r4
-; MIR32:   renamable $r4 = LI 16
-; MIR32:   renamable $v3 = LVX renamable $r3, killed renamable $r4
-; MIR32:   renamable $v4 = LVSL $zero, renamable $r3
-; MIR32:   renamable $v2 = VPERM renamable $v3, killed renamable $v2, renamable $v4
-; MIR32:   renamable $r4 = LI 172
-; MIR32:   STXVW4X killed renamable $v2, $r1, killed renamable $r4 :: (store (s128) into unknown-address + 16, align 4)
-; MIR32:   renamable $v2 = LVX $zero, killed renamable $r3
-; MIR32:   renamable $v2 = VPERM killed renamable $v2, killed renamable $v3, killed renamable $v4
-; MIR32:   renamable $r3 = LI 156
-; MIR32:   STXVW4X killed renamable $v2, $r1, killed renamable $r3 :: (store (s128), align 4)
-; MIR32:   ADJCALLSTACKDOWN 188, 0, implicit-def dead $r1, implicit $r1
-; MIR32:   renamable $vsl0 = XXLXORz
-; MIR32:   $f1 = XXLXORdpz
-; MIR32:   $f2 = XXLXORdpz
-; MIR32:   $v2 = XXLXORz
-; MIR32:   $v3 = XXLXORz
-; MIR32:   $v4 = XXLXORz
-; MIR32:   $v5 = XXLXORz
-; MIR32:   $v6 = XXLXORz
-; MIR32:   $v7 = XXLXORz
-; MIR32:   $v8 = XXLXORz
-; MIR32:   $v9 = XXLXORz
-; MIR32:   $v10 = XXLXORz
-; MIR32:   $v11 = XXLXORz
-; MIR32:   $v12 = XXLXORz
-; MIR32:   $v13 = XXLXORz
-; MIR32:   $f3 = XXLXORdpz
-; MIR32:   $f4 = XXLXORdpz
-; MIR32:   $f5 = XXLXORdpz
-; MIR32:   $f6 = XXLXORdpz
-; MIR32:   $f7 = XXLXORdpz
-; MIR32:   renamable $r3 = LI 136
-; MIR32:   $f8 = XXLXORdpz
-; MIR32:   renamable $r4 = LI 120
-; MIR32:   renamable $r5 = LWZtoc %const.0, $r2 :: (load (s32) from got)
-; MIR32:   STXVW4X renamable $vsl0, $r1, killed renamable $r3 :: (store (s128), align 8)
-; MIR32:   $f9 = XXLXORdpz
-; MIR32:   renamable $r3 = LI 104
-; MIR32:   STXVW4X renamable $vsl0, $r1, killed renamable $r4 :: (store (s128), align 8)
-; MIR32:   $f10 = XXLXORdpz
-; MIR32:   STXVW4X renamable $vsl0, $r1, killed renamable $r3 :: (store (s128), align 8)
-; MIR32:   renamable $r3 = LI 88
-; MIR32:   $f11 = XXLXORdpz
-; MIR32:   STXVW4X renamable $vsl0, $r1, killed renamable $r3 :: (store (s128), align 8)
-; MIR32:   renamable $r3 = LI 72
-; MIR32:   renamable $v0 = LXVD2X $zero, killed renamable $r5 :: (load (s128) from constant-pool)
-; MIR32:   $f12 = XXLXORdpz
-; MIR32:   STXVW4X killed renamable $vsl0, $r1, killed renamable $r3 :: (store (s128), align 8)
-; MIR32:   $f13 = XXLXORdpz
-; MIR32:   renamable $r5 = LI 48
-; MIR32:   renamable $r6 = LI 512
-; MIR32:   $r3 = LI 128
-; MIR32:   $r4 = LI 256
-; MIR32:   STXVD2X killed renamable $v0, $r1, killed renamable $r5 :: (store (s128))
-; MIR32:   STW killed renamable $r6, 152, $r1 :: (store (s32))
-; MIR32:   BL_NOP <mcsymbol .callee[PR]>, csr_aix32_altivec, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $f1, implicit $f2, implicit $v2, implicit $v3, implicit $v4, implicit $v5, implicit killed $v6, implicit killed $v7, implicit killed $v8, implicit killed $v9, implicit killed $v10, implicit killed $v11, implicit killed $v12, implicit killed $v13, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $r2, implicit-def $r1, implicit-def $f1
-; MIR32:   ADJCALLSTACKUP 188, 0, implicit-def dead $r1, implicit $r1
-; MIR32:   BLR implicit $lr, implicit $rm, implicit $f1
 
+  ; MIR32-LABEL: name: caller
----------------
Why are the lines indented?


================
Comment at: llvm/test/CodeGen/PowerPC/build-vector-allones.ll:36
 ; P7BE:       # %bb.0: # %entry
-; P7BE-NEXT:    addis r3, r2, .LCPI1_0 at toc@ha
-; P7BE-NEXT:    addi r3, r3, .LCPI1_0 at toc@l
-; P7BE-NEXT:    lxvd2x vs34, 0, r3
+; P7BE-NEXT:    vspltisb
 ; P7BE-NEXT:    blr
----------------
The operands are scrubbed. Maybe the script needs fix.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D105596/new/

https://reviews.llvm.org/D105596