[llvm] 89f2d98 - [PowerPC] Add P7 RUN line for load and splat test
Jinsong Ji via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 7 14:43:58 PDT 2021
Author: Jinsong Ji
Date: 2021-07-07T21:43:46Z
New Revision: 89f2d98b9870263106adfeb20c835d4751963cf7
URL: https://github.com/llvm/llvm-project/commit/89f2d98b9870263106adfeb20c835d4751963cf7
DIFF: https://github.com/llvm/llvm-project/commit/89f2d98b9870263106adfeb20c835d4751963cf7.diff
LOG: [PowerPC] Add P7 RUN line for load and splat test
Added:
Modified:
llvm/test/CodeGen/PowerPC/load-and-splat.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/PowerPC/load-and-splat.ll b/llvm/test/CodeGen/PowerPC/load-and-splat.ll
index c011e4541204..3ec8468dcd36 100644
--- a/llvm/test/CodeGen/PowerPC/load-and-splat.ll
+++ b/llvm/test/CodeGen/PowerPC/load-and-splat.ll
@@ -5,6 +5,10 @@
; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
; RUN: -check-prefix=P8
+; RUN: llc -mcpu=pwr7 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
+; RUN: -check-prefix=P7
+
define dso_local void @test(<2 x double>* nocapture %c, double* nocapture readonly %a) local_unnamed_addr {
; P9-LABEL: test:
; P9: # %bb.0: # %entry
@@ -19,6 +23,13 @@ define dso_local void @test(<2 x double>* nocapture %c, double* nocapture readon
; P8-NEXT: lxvdsx vs0, 0, r4
; P8-NEXT: stxvd2x vs0, 0, r3
; P8-NEXT: blr
+;
+; P7-LABEL: test:
+; P7: # %bb.0: # %entry
+; P7-NEXT: addi r4, r4, 24
+; P7-NEXT: lxvdsx vs0, 0, r4
+; P7-NEXT: stxvd2x vs0, 0, r3
+; P7-NEXT: blr
entry:
%arrayidx = getelementptr inbounds double, double* %a, i64 3
%0 = load double, double* %arrayidx, align 8
@@ -43,6 +54,16 @@ define dso_local void @test2(<4 x float>* nocapture %c, float* nocapture readonl
; P8-NEXT: xxspltw v2, vs0, 1
; P8-NEXT: stvx v2, 0, r3
; P8-NEXT: blr
+;
+; P7-LABEL: test2:
+; P7: # %bb.0: # %entry
+; P7-NEXT: lwz r4, 12(r4)
+; P7-NEXT: addi r5, r1, -16
+; P7-NEXT: stw r4, -16(r1)
+; P7-NEXT: lxvw4x vs0, 0, r5
+; P7-NEXT: xxspltw vs0, vs0, 0
+; P7-NEXT: stxvw4x vs0, 0, r3
+; P7-NEXT: blr
entry:
%arrayidx = getelementptr inbounds float, float* %a, i64 3
%0 = load float, float* %arrayidx, align 4
@@ -67,6 +88,16 @@ define dso_local void @test3(<4 x i32>* nocapture %c, i32* nocapture readonly %a
; P8-NEXT: xxspltw v2, vs0, 1
; P8-NEXT: stvx v2, 0, r3
; P8-NEXT: blr
+;
+; P7-LABEL: test3:
+; P7: # %bb.0: # %entry
+; P7-NEXT: lwz r4, 12(r4)
+; P7-NEXT: addi r5, r1, -16
+; P7-NEXT: stw r4, -16(r1)
+; P7-NEXT: lxvw4x vs0, 0, r5
+; P7-NEXT: xxspltw vs0, vs0, 0
+; P7-NEXT: stxvw4x vs0, 0, r3
+; P7-NEXT: blr
entry:
%arrayidx = getelementptr inbounds i32, i32* %a, i64 3
%0 = load i32, i32* %arrayidx, align 4
@@ -90,6 +121,16 @@ define dso_local void @test4(<2 x i64>* nocapture %c, i64* nocapture readonly %a
; P8-NEXT: lxvdsx vs0, 0, r4
; P8-NEXT: stxvd2x vs0, 0, r3
; P8-NEXT: blr
+;
+; P7-LABEL: test4:
+; P7: # %bb.0: # %entry
+; P7-NEXT: ld r4, 24(r4)
+; P7-NEXT: addi r5, r1, -16
+; P7-NEXT: std r4, -8(r1)
+; P7-NEXT: std r4, -16(r1)
+; P7-NEXT: lxvd2x vs0, 0, r5
+; P7-NEXT: stxvd2x vs0, 0, r3
+; P7-NEXT: blr
entry:
%arrayidx = getelementptr inbounds i64, i64* %a, i64 3
%0 = load i64, i64* %arrayidx, align 8
@@ -110,6 +151,15 @@ define <16 x i8> @unadjusted_lxvwsx(i32* %s, i32* %t) {
; P8-NEXT: lfiwzx f0, 0, r3
; P8-NEXT: xxspltw v2, vs0, 1
; P8-NEXT: blr
+;
+; P7-LABEL: unadjusted_lxvwsx:
+; P7: # %bb.0: # %entry
+; P7-NEXT: lwz r3, 0(r3)
+; P7-NEXT: addi r4, r1, -16
+; P7-NEXT: stw r3, -16(r1)
+; P7-NEXT: lxvw4x vs0, 0, r4
+; P7-NEXT: xxspltw v2, vs0, 0
+; P7-NEXT: blr
entry:
%0 = bitcast i32* %s to <4 x i8>*
%1 = load <4 x i8>, <4 x i8>* %0, align 4
@@ -129,6 +179,15 @@ define <16 x i8> @adjusted_lxvwsx(i64* %s, i64* %t) {
; P8-NEXT: lfdx f0, 0, r3
; P8-NEXT: xxspltw v2, vs0, 0
; P8-NEXT: blr
+;
+; P7-LABEL: adjusted_lxvwsx:
+; P7: # %bb.0: # %entry
+; P7-NEXT: ld r3, 0(r3)
+; P7-NEXT: addi r4, r1, -16
+; P7-NEXT: std r3, -16(r1)
+; P7-NEXT: lxvw4x vs0, 0, r4
+; P7-NEXT: xxspltw v2, vs0, 1
+; P7-NEXT: blr
entry:
%0 = bitcast i64* %s to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8
@@ -147,6 +206,12 @@ define <16 x i8> @unadjusted_lxvwsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
; P8-NEXT: lvx v2, 0, r3
; P8-NEXT: xxspltw v2, v2, 3
; P8-NEXT: blr
+;
+; P7-LABEL: unadjusted_lxvwsx_v16i8:
+; P7: # %bb.0: # %entry
+; P7-NEXT: lxvw4x vs0, 0, r3
+; P7-NEXT: xxspltw v2, vs0, 0
+; P7-NEXT: blr
entry:
%0 = load <16 x i8>, <16 x i8>* %s, align 16
%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
@@ -165,6 +230,12 @@ define <16 x i8> @adjusted_lxvwsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
; P8-NEXT: lvx v2, 0, r3
; P8-NEXT: xxspltw v2, v2, 2
; P8-NEXT: blr
+;
+; P7-LABEL: adjusted_lxvwsx_v16i8:
+; P7: # %bb.0: # %entry
+; P7-NEXT: lxvw4x vs0, 0, r3
+; P7-NEXT: xxspltw v2, vs0, 1
+; P7-NEXT: blr
entry:
%0 = load <16 x i8>, <16 x i8>* %s, align 16
%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
@@ -183,6 +254,12 @@ define <16 x i8> @adjusted_lxvwsx_v16i8_2(<16 x i8> *%s, <16 x i8> %t) {
; P8-NEXT: lvx v2, 0, r3
; P8-NEXT: xxspltw v2, v2, 1
; P8-NEXT: blr
+;
+; P7-LABEL: adjusted_lxvwsx_v16i8_2:
+; P7: # %bb.0: # %entry
+; P7-NEXT: lxvw4x vs0, 0, r3
+; P7-NEXT: xxspltw v2, vs0, 2
+; P7-NEXT: blr
entry:
%0 = load <16 x i8>, <16 x i8>* %s, align 16
%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11>
@@ -201,6 +278,12 @@ define <16 x i8> @adjusted_lxvwsx_v16i8_3(<16 x i8> *%s, <16 x i8> %t) {
; P8-NEXT: lvx v2, 0, r3
; P8-NEXT: xxspltw v2, v2, 0
; P8-NEXT: blr
+;
+; P7-LABEL: adjusted_lxvwsx_v16i8_3:
+; P7: # %bb.0: # %entry
+; P7-NEXT: lxvw4x vs0, 0, r3
+; P7-NEXT: xxspltw v2, vs0, 3
+; P7-NEXT: blr
entry:
%0 = load <16 x i8>, <16 x i8>* %s, align 16
%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
@@ -217,6 +300,11 @@ define <16 x i8> @unadjusted_lxvdsx(i64* %s, i64* %t) {
; P8: # %bb.0: # %entry
; P8-NEXT: lxvdsx v2, 0, r3
; P8-NEXT: blr
+;
+; P7-LABEL: unadjusted_lxvdsx:
+; P7: # %bb.0: # %entry
+; P7-NEXT: lxvdsx v2, 0, r3
+; P7-NEXT: blr
entry:
%0 = bitcast i64* %s to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8
@@ -234,6 +322,11 @@ define <16 x i8> @unadjusted_lxvdsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
; P8: # %bb.0: # %entry
; P8-NEXT: lxvdsx v2, 0, r3
; P8-NEXT: blr
+;
+; P7-LABEL: unadjusted_lxvdsx_v16i8:
+; P7: # %bb.0: # %entry
+; P7-NEXT: lxvdsx v2, 0, r3
+; P7-NEXT: blr
entry:
%0 = load <16 x i8>, <16 x i8>* %s, align 16
%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
@@ -252,6 +345,12 @@ define <16 x i8> @adjusted_lxvdsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
; P8-NEXT: addi r3, r3, 8
; P8-NEXT: lxvdsx v2, 0, r3
; P8-NEXT: blr
+;
+; P7-LABEL: adjusted_lxvdsx_v16i8:
+; P7: # %bb.0: # %entry
+; P7-NEXT: addi r3, r3, 8
+; P7-NEXT: lxvdsx v2, 0, r3
+; P7-NEXT: blr
entry:
%0 = load <16 x i8>, <16 x i8>* %s, align 16
%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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