[llvm] ee6ca9c - [AIX] Use VSSRC/VSFRC Register classes for f32/f64 callee arguments on P8 and above
Zarko Todorovski via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 7 06:18:26 PDT 2021
Author: Zarko Todorovski
Date: 2021-07-07T09:18:20-04:00
New Revision: ee6ca9c7dfd900b2906e5e457666287212b2c378
URL: https://github.com/llvm/llvm-project/commit/ee6ca9c7dfd900b2906e5e457666287212b2c378
DIFF: https://github.com/llvm/llvm-project/commit/ee6ca9c7dfd900b2906e5e457666287212b2c378.diff
LOG: [AIX] Use VSSRC/VSFRC Register classes for f32/f64 callee arguments on P8 and above
Adding usage of VSSRC and VSFRC when adding the live in registers on AIX.
This matches the behaviour of the rest of PPC Subtargets.
Reviewed By: nemanjai, #powerpc
Differential Revision: https://reviews.llvm.org/D104396
Added:
llvm/test/CodeGen/PowerPC/aix-p8vector-liveins.ll
Modified:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 9383f67e3f6b..bb3121905993 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -6738,8 +6738,11 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
return true;
}
+// So far, this function is only used by LowerFormalArguments_AIX()
static const TargetRegisterClass *getRegClassForSVT(MVT::SimpleValueType SVT,
- bool IsPPC64) {
+ bool IsPPC64,
+ bool HasP8Vector,
+ bool HasVSX) {
assert((IsPPC64 || SVT != MVT::i64) &&
"i64 should have been split for 32-bit codegen.");
@@ -6751,9 +6754,9 @@ static const TargetRegisterClass *getRegClassForSVT(MVT::SimpleValueType SVT,
case MVT::i64:
return IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
case MVT::f32:
- return &PPC::F4RCRegClass;
+ return HasP8Vector ? &PPC::VSSRCRegClass : &PPC::F4RCRegClass;
case MVT::f64:
- return &PPC::F8RCRegClass;
+ return HasVSX ? &PPC::VSFRCRegClass : &PPC::F8RCRegClass;
case MVT::v4f32:
case MVT::v4i32:
case MVT::v8i16:
@@ -6929,7 +6932,9 @@ SDValue PPCTargetLowering::LowerFormalArguments_AIX(
assert(VA.getValNo() == OriginalValNo &&
"ValNo mismatch between custom MemLoc and RegLoc.");
MVT::SimpleValueType SVT = VA.getLocVT().SimpleTy;
- MF.addLiveIn(VA.getLocReg(), getRegClassForSVT(SVT, IsPPC64));
+ MF.addLiveIn(VA.getLocReg(),
+ getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(),
+ Subtarget.hasVSX()));
};
HandleMemLoc();
@@ -7068,8 +7073,10 @@ SDValue PPCTargetLowering::LowerFormalArguments_AIX(
if (VA.isRegLoc() && !VA.needsCustom()) {
MVT::SimpleValueType SVT = ValVT.SimpleTy;
- unsigned VReg =
- MF.addLiveIn(VA.getLocReg(), getRegClassForSVT(SVT, IsPPC64));
+ Register VReg =
+ MF.addLiveIn(VA.getLocReg(),
+ getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(),
+ Subtarget.hasVSX()));
SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
if (ValVT.isScalarInteger() &&
(ValVT.getFixedSizeInBits() < LocVT.getFixedSizeInBits())) {
diff --git a/llvm/test/CodeGen/PowerPC/aix-p8vector-liveins.ll b/llvm/test/CodeGen/PowerPC/aix-p8vector-liveins.ll
new file mode 100644
index 000000000000..07ec88840dc3
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/aix-p8vector-liveins.ll
@@ -0,0 +1,115 @@
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 \
+; RUN: -verify-machineinstrs -stop-after=finalize-isel < %s | \
+; RUN: FileCheck --check-prefixes=POWR8,VSX %s
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr7 \
+; RUN: -verify-machineinstrs -mattr=-vsx -stop-after=finalize-isel \
+; RUN: < %s | FileCheck %s --check-prefixes=NOVSX,NOP8V
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr7 \
+; RUN: -verify-machineinstrs -mattr=vsx -stop-after=finalize-isel \
+; RUN: < %s | FileCheck %s --check-prefixes=VSX,NOP8V
+
+define float @vssr(float %a, float %b, float %c, float %d, float %e) {
+entry:
+ %add = fadd float %a, %b
+ %add1 = fadd float %add, %c
+ %add2 = fadd float %add1, %d
+ %add3 = fadd float %add2, %e
+ ret float %add3
+}
+
+; POWR8-LABEL: name: vssr
+; POWR8: - { id: 0, class: vssrc, preferred-register: '' }
+; POWR8: - { id: 1, class: vssrc, preferred-register: '' }
+; POWR8: - { id: 2, class: vssrc, preferred-register: '' }
+; POWR8: - { id: 3, class: vssrc, preferred-register: '' }
+; POWR8: - { id: 4, class: vssrc, preferred-register: '' }
+; POWR8: - { id: 5, class: vssrc, preferred-register: '' }
+; POWR8: - { id: 6, class: vssrc, preferred-register: '' }
+; POWR8: - { id: 7, class: vssrc, preferred-register: '' }
+; POWR8: - { id: 8, class: vssrc, preferred-register: '' }
+; POWR8: %4:vssrc = COPY $f5
+; POWR8: %3:vssrc = COPY $f4
+; POWR8: %2:vssrc = COPY $f3
+; POWR8: %1:vssrc = COPY $f2
+; POWR8: %0:vssrc = COPY $f1
+; POWR8: %5:vssrc = nofpexcept XSADDSP %0, %1
+; POWR8: %6:vssrc = nofpexcept XSADDSP killed %5, %2
+; POWR8: %7:vssrc = nofpexcept XSADDSP killed %6, %3
+; POWR8: %8:vssrc = nofpexcept XSADDSP killed %7, %4
+; POWR8: $f1 = COPY %8
+
+; NOP8V-LABEL: name: vssr
+; NOP8V: registers:
+; NOP8V: - { id: 0, class: f4rc, preferred-register: '' }
+; NOP8V: - { id: 1, class: f4rc, preferred-register: '' }
+; NOP8V: - { id: 2, class: f4rc, preferred-register: '' }
+; NOP8V: - { id: 3, class: f4rc, preferred-register: '' }
+; NOP8V: - { id: 4, class: f4rc, preferred-register: '' }
+; NOP8V: - { id: 5, class: f4rc, preferred-register: '' }
+; NOP8V: - { id: 6, class: f4rc, preferred-register: '' }
+; NOP8V: - { id: 7, class: f4rc, preferred-register: '' }
+; NOP8V: - { id: 8, class: f4rc, preferred-register: '' }
+; NOP8V: %4:f4rc = COPY $f5
+; NOP8V: %3:f4rc = COPY $f4
+; NOP8V: %2:f4rc = COPY $f3
+; NOP8V: %1:f4rc = COPY $f2
+; NOP8V: %0:f4rc = COPY $f1
+; NOP8V: %5:f4rc = nofpexcept FADDS %0, %1, implicit $rm
+; NOP8V: %6:f4rc = nofpexcept FADDS killed %5, %2, implicit $rm
+; NOP8V: %7:f4rc = nofpexcept FADDS killed %6, %3, implicit $rm
+; NOP8V: %8:f4rc = nofpexcept FADDS killed %7, %4, implicit $rm
+; NOP8V: $f1 = COPY %8
+
+define double @vsfr(double %a, double %b, double %c, double %d, double %e) {
+entry:
+ %add = fadd double %a, %b
+ %add1 = fadd double %add, %c
+ %add2 = fadd double %add1, %d
+ %add3 = fadd double %add2, %e
+ ret double %add3
+}
+
+; VSX-LABEL: vsfr
+; VSX: registers:
+; VSX: - { id: 0, class: vsfrc, preferred-register: '' }
+; VSX: - { id: 1, class: vsfrc, preferred-register: '' }
+; VSX: - { id: 2, class: vsfrc, preferred-register: '' }
+; VSX: - { id: 3, class: vsfrc, preferred-register: '' }
+; VSX: - { id: 4, class: vsfrc, preferred-register: '' }
+; VSX: - { id: 5, class: vsfrc, preferred-register: '' }
+; VSX: - { id: 6, class: vsfrc, preferred-register: '' }
+; VSX: - { id: 7, class: vsfrc, preferred-register: '' }
+; VSX: - { id: 8, class: vsfrc, preferred-register: '' }
+; VSX: %4:vsfrc = COPY $f5
+; VSX: %3:vsfrc = COPY $f4
+; VSX: %2:vsfrc = COPY $f3
+; VSX: %1:vsfrc = COPY $f2
+; VSX: %0:vsfrc = COPY $f1
+; VSX: %5:vsfrc = nofpexcept XSADDDP %0, %1, implicit $rm
+; VSX: %6:vsfrc = nofpexcept XSADDDP killed %5, %2, implicit $rm
+; VSX: %7:vsfrc = nofpexcept XSADDDP killed %6, %3, implicit $rm
+; VSX: %8:vsfrc = nofpexcept XSADDDP killed %7, %4, implicit $rm
+; VSX: $f1 = COPY %8
+
+; NOVSX-LABEL: vsfr
+; NOVSX: registers:
+; NOVSX: - { id: 0, class: f8rc, preferred-register: '' }
+; NOVSX: - { id: 1, class: f8rc, preferred-register: '' }
+; NOVSX: - { id: 2, class: f8rc, preferred-register: '' }
+; NOVSX: - { id: 3, class: f8rc, preferred-register: '' }
+; NOVSX: - { id: 4, class: f8rc, preferred-register: '' }
+; NOVSX: - { id: 5, class: f8rc, preferred-register: '' }
+; NOVSX: - { id: 6, class: f8rc, preferred-register: '' }
+; NOVSX: - { id: 7, class: f8rc, preferred-register: '' }
+; NOVSX: - { id: 8, class: f8rc, preferred-register: '' }
+; NOVSX: %4:f8rc = COPY $f5
+; NOVSX: %3:f8rc = COPY $f4
+; NOVSX: %2:f8rc = COPY $f3
+; NOVSX: %1:f8rc = COPY $f2
+; NOVSX: %0:f8rc = COPY $f1
+; NOVSX: %5:f8rc = nofpexcept FADD %0, %1, implicit $rm
+; NOVSX: %6:f8rc = nofpexcept FADD killed %5, %2, implicit $rm
+; NOVSX: %7:f8rc = nofpexcept FADD killed %6, %3, implicit $rm
+; NOVSX: %8:f8rc = nofpexcept FADD killed %7, %4, implicit $rm
+; NOVSX: $f1 = COPY %8
+
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