[PATCH] D105541: [AArch64] Set the latency of A55 stores to 1

Dave Green via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jul 7 02:50:20 PDT 2021


dmgreen created this revision.
dmgreen added reviewers: NickGuy, andreadb, asavonic.
Herald added subscribers: danielkiss, gbedwell, hiraditya, kristof.beyls.
dmgreen requested review of this revision.
Herald added a project: LLVM.

This sets the latency of stores to 1 in the Cortex-A55 scheduling model, to better match the values given in the software optimization guide.

The latency of a store in normal llvm scheduling does not appear to have a lot of uses. If the store has no output's then the latency is somewhat meaningless (and pre/post increment update operands use the WriteAdr write for those operands instead). The one place it does alter things is the latency between a store and the end of the scheduling region, which can in turn have an effect on the critical path length. As a result a latency of 1 is more correct and offers ever-so-slightly better scheduling of instructions near the end of the block.

They are marked as RetireOOO to keep the llvm-mca from introducing stalls where non would exist.


https://reviews.llvm.org/D105541

Files:
  llvm/lib/Target/AArch64/AArch64SchedA55.td
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-stats.s
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-all-views.s
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-basic-instructions.s
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-in-order-retire.s
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-load-store-alias.s
  llvm/test/tools/llvm-mca/AArch64/Cortex/A55-out-of-order-retire.s

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