[llvm] 56b3e9e - [AArch64] Sync isDef32 to the current x86 version.

[Eli Friedman via llvm-commits]

Author: Eli Friedman
Date: 2021-07-06T17:05:01-07:00
New Revision: 56b3e9edc49314e874c9d52e9d5f5cf08f62c948

URL: https://github.com/llvm/llvm-project/commit/56b3e9edc49314e874c9d52e9d5f5cf08f62c948
DIFF: https://github.com/llvm/llvm-project/commit/56b3e9edc49314e874c9d52e9d5f5cf08f62c948.diff

LOG: [AArch64] Sync isDef32 to the current x86 version.

We should probably come up with some better way to do this, but let's
make sure to catch known issues for now.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.h

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index 392910560eff..a0be2d52ef14 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -449,12 +449,12 @@ namespace {
 // be copying from a truncate. But any other 32-bit operation will zero-extend
 // up to 64 bits. AssertSext/AssertZext aren't saying anything about the upper
 // 32 bits, they're probably just qualifying a CopyFromReg.
-// FIXME: X86 also checks for CMOV here. Do we need something similar?
 static inline bool isDef32(const SDNode &N) {
   unsigned Opc = N.getOpcode();
   return Opc != ISD::TRUNCATE && Opc != TargetOpcode::EXTRACT_SUBREG &&
          Opc != ISD::CopyFromReg && Opc != ISD::AssertSext &&
-         Opc != ISD::AssertZext;
+         Opc != ISD::AssertZext && Opc != ISD::AssertAlign &&
+         Opc != ISD::FREEZE;
 }
 
 } // end anonymous namespace