[llvm] 5915d33 - [AMDGPU] Do not run IR optimizations at -O0

[Stanislav Mekhanoshin via llvm-commits]

Author: Stanislav Mekhanoshin
Date: 2021-07-06T15:29:52-07:00
New Revision: 5915d33874fd0278f72f2c1a8cf2047bdf0ffd31

URL: https://github.com/llvm/llvm-project/commit/5915d33874fd0278f72f2c1a8cf2047bdf0ffd31
DIFF: https://github.com/llvm/llvm-project/commit/5915d33874fd0278f72f2c1a8cf2047bdf0ffd31.diff

LOG: [AMDGPU] Do not run IR optimizations at -O0

Differential Revision: https://reviews.llvm.org/D105515

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    llvm/test/CodeGen/AMDGPU/llc-pipeline.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index a34449c57b3d..395672f7b5c9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -940,11 +940,11 @@ void AMDGPUPassConfig::addIRPasses() {
           AAR.addAAResult(WrapperPass->getResult());
         }));
     }
-  }
 
-  if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
-    // TODO: May want to move later or split into an early and late one.
-    addPass(createAMDGPUCodeGenPreparePass());
+    if (TM.getTargetTriple().getArch() == Triple::amdgcn) {
+      // TODO: May want to move later or split into an early and late one.
+      addPass(createAMDGPUCodeGenPreparePass());
+    }
   }
 
   TargetPassConfig::addIRPasses();
@@ -1062,7 +1062,9 @@ ScheduleDAGInstrs *GCNPassConfig::createMachineScheduler(
 bool GCNPassConfig::addPreISel() {
   AMDGPUPassConfig::addPreISel();
 
-  addPass(createAMDGPULateCodeGenPreparePass());
+  if (TM->getOptLevel() > CodeGenOpt::None)
+    addPass(createAMDGPULateCodeGenPreparePass());
+
   if (EnableAtomicOptimizations) {
     addPass(createAMDGPUAtomicOptimizerPass());
   }

diff  --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
index 1f1609c8b68d..b62d6905d047 100644
--- a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
+++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
@@ -44,11 +44,6 @@
 ; GCN-O0-NEXT:     Lower OpenCL enqueued blocks
 ; GCN-O0-NEXT:     Lower uses of LDS variables from non-kernel functions
 ; GCN-O0-NEXT:     FunctionPass Manager
-; GCN-O0-NEXT:       Dominator Tree Construction
-; GCN-O0-NEXT:       Post-Dominator Tree Construction
-; GCN-O0-NEXT:       Natural Loop Information
-; GCN-O0-NEXT:       Legacy Divergence Analysis
-; GCN-O0-NEXT:       AMDGPU IR optimizations
 ; GCN-O0-NEXT:       Lower Garbage Collection Instructions
 ; GCN-O0-NEXT:       Shadow Stack GC Lowering
 ; GCN-O0-NEXT:       Lower constant intrinsics
@@ -72,13 +67,11 @@
 ; GCN-O0-NEXT:       Function Alias Analysis Results
 ; GCN-O0-NEXT:       Flatten the CFG
 ; GCN-O0-NEXT:       Dominator Tree Construction
-; GCN-O0-NEXT:       Post-Dominator Tree Construction
-; GCN-O0-NEXT:       Natural Loop Information
-; GCN-O0-NEXT:       Legacy Divergence Analysis
-; GCN-O0-NEXT:       AMDGPU IR late optimizations
 ; GCN-O0-NEXT:       Basic Alias Analysis (stateless AA impl)
 ; GCN-O0-NEXT:       Function Alias Analysis Results
+; GCN-O0-NEXT:       Natural Loop Information
 ; GCN-O0-NEXT:       Code sinking
+; GCN-O0-NEXT:       Post-Dominator Tree Construction
 ; GCN-O0-NEXT:       Legacy Divergence Analysis
 ; GCN-O0-NEXT:       Unify divergent function exit nodes
 ; GCN-O0-NEXT:       Lazy Value Information Analysis