[PATCH] D103614: [PowerPC] Generate inlined quadword lock free atomic operations via AtomicExpand

[Kai Luo via Phabricator via llvm-commits]

lkail updated this revision to Diff 356699.
lkail retitled this revision from "[PowerPC][AIX] Generate inlined quadword lock free atomic operations via AtomicExpand" to "[PowerPC] Generate inlined quadword lock free atomic operations via AtomicExpand".
lkail added a comment.

I had an internal discussion with @hubert.reinterpretcast and @jsji after reviewing https://reviews.llvm.org/D103501, considering AIX current doesn't support `__int128_t` which is required in compiler-rt's atomic implementation, we don't enable quadword lock-free atomics by default on AIX.

Updated:

- Add `-ppc-quadword-atomics` switch
- Add `cmpxchg` support

I'll post another patch for atomic load/store.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103614/new/

https://reviews.llvm.org/D103614

Files:
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/CodeGen/AtomicExpandPass.cpp
  llvm/lib/Target/PowerPC/CMakeLists.txt
  llvm/lib/Target/PowerPC/PPC.h
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCExpandAtomicPseudoInsts.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCSubtarget.h
  llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
  llvm/test/CodeGen/PowerPC/O3-pipeline.ll
  llvm/test/CodeGen/PowerPC/atomics-i128.ll

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