[PATCH] D105390: [X86] Lower insertions into upper half of an 256-bit vector as broadcast+blend (PR50971)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:18963
 
+    unsigned NumEltsIn128 = 128 / EltSizeInBits;
+
----------------
Move the assert(isPowerOf2_32(NumEltsIn128)) as well? And add an assert message to match style guide.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:18969
+        ((Subtarget.hasAVX2() && EltVT != MVT::i8) ||
+         (N1.hasOneUse() && N1.getOpcode() == ISD::LOAD && Subtarget.hasAVX() &&
+          (EltSizeInBits == 32 || EltSizeInBits == 64)))) {
----------------
Use MayFoldLoad?


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:37551
+        isNullConstant(Src.getOperand(1)))
+      return DAG.getNode(X86ISD::VBROADCAST, DL, VT, Src.getOperand(0));
+
----------------
We might need a legal type check on Src.getOperand(0) before introducing a target opcode?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105390/new/

https://reviews.llvm.org/D105390