[PATCH] D105235: [AMDGPU] Fix immediate sign during V_MOV_B64_PSEUDO expansion

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

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Creating a V_MOV_B32 with zero extended immediate source
prevented conversion to V_BFREV_B32.


https://reviews.llvm.org/D105235

Files:
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/test/CodeGen/AMDGPU/v_mov_b64_expand_and_shrink.mir
  llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir


Index: llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir
+++ llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir
@@ -22,10 +22,10 @@
 ...
 
 # GCN-LABEL: name: v_mov_b64_from_sext_inline_imm
-# GFX900: $vgpr0 = V_MOV_B32_e32 4294967294, implicit $exec, implicit-def $vgpr0_vgpr1
-# GFX900: $vgpr1 = V_MOV_B32_e32 4294967295, implicit $exec, implicit-def $vgpr0_vgpr1
-# GFX90A: $vgpr0 = V_MOV_B32_e32 4294967294, implicit $exec, implicit-def $vgpr0_vgpr1
-# GFX90A: $vgpr1 = V_MOV_B32_e32 4294967295, implicit $exec, implicit-def $vgpr0_vgpr1
+# GFX900: $vgpr0 = V_MOV_B32_e32 -2, implicit $exec, implicit-def $vgpr0_vgpr1
+# GFX900: $vgpr1 = V_MOV_B32_e32 -1, implicit $exec, implicit-def $vgpr0_vgpr1
+# GFX90A: $vgpr0 = V_MOV_B32_e32 -2, implicit $exec, implicit-def $vgpr0_vgpr1
+# GFX90A: $vgpr1 = V_MOV_B32_e32 -1, implicit $exec, implicit-def $vgpr0_vgpr1
 name: v_mov_b64_from_sext_inline_imm
 body: |
   bb.0:
@@ -34,7 +34,7 @@
 
 # GCN-LABEL: name: v_mov_b64_from_lit
 # GCN: $vgpr0 = V_MOV_B32_e32 1430494974, implicit $exec, implicit-def $vgpr0_vgpr1
-# GCN: $vgpr1 = V_MOV_B32_e32 4294734465, implicit $exec, implicit-def $vgpr0_vgpr1
+# GCN: $vgpr1 = V_MOV_B32_e32 -232831, implicit $exec, implicit-def $vgpr0_vgpr1
 name: v_mov_b64_from_lit
 body: |
   bb.0:
@@ -42,7 +42,7 @@
 ...
 
 # GCN-LABEL: name: v_mov_b64_from_first_inline_imm
-# GCN: $vgpr0 = V_MOV_B32_e32 4294967295, implicit $exec, implicit-def $vgpr0_vgpr1
+# GCN: $vgpr0 = V_MOV_B32_e32 -1, implicit $exec, implicit-def $vgpr0_vgpr1
 # GCN: $vgpr1 = V_MOV_B32_e32 268435455, implicit $exec, implicit-def $vgpr0_vgpr1
 name: v_mov_b64_from_first_inline_imm
 body: |
@@ -52,7 +52,7 @@
 
 # GCN-LABEL: name: v_mov_b64_from_second_inline_imm
 # GCN: $vgpr0 = V_MOV_B32_e32 268435455, implicit $exec, implicit-def $vgpr0_vgpr1
-# GCN: $vgpr1 = V_MOV_B32_e32 4294967295, implicit $exec, implicit-def $vgpr0_vgpr1
+# GCN: $vgpr1 = V_MOV_B32_e32 -1, implicit $exec, implicit-def $vgpr0_vgpr1
 name: v_mov_b64_from_second_inline_imm
 body: |
   bb.0:
@@ -60,8 +60,8 @@
 ...
 
 # GCN-LABEL: name: v_mov_b64_from_same_sext_inline_imm
-# GFX900: $vgpr0 = V_MOV_B32_e32 4294967295, implicit $exec, implicit-def $vgpr0_vgpr1
-# GFX900: $vgpr1 = V_MOV_B32_e32 4294967295, implicit $exec, implicit-def $vgpr0_vgpr1
+# GFX900: $vgpr0 = V_MOV_B32_e32 -1, implicit $exec, implicit-def $vgpr0_vgpr1
+# GFX900: $vgpr1 = V_MOV_B32_e32 -1, implicit $exec, implicit-def $vgpr0_vgpr1
 # GFX90A: $vgpr0_vgpr1 = V_PK_MOV_B32 8, -1, 8, -1, 0, 0, 0, 0, 0, implicit $exec
 name: v_mov_b64_from_same_sext_inline_imm
 body: |
Index: llvm/test/CodeGen/AMDGPU/v_mov_b64_expand_and_shrink.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/v_mov_b64_expand_and_shrink.mir
@@ -0,0 +1,12 @@
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass postrapseudos,si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+
+---
+# GCN-LABEL: name: expand_imm64_sext_shrink_to_bfrev
+# GCN: $vgpr0 = V_MOV_B32_e32 0, implicit $exec, implicit-def $vgpr0_vgpr1
+# GCN: $vgpr1 = V_BFREV_B32_e32 1, implicit $exec, implicit-def $vgpr0_vgpr1
+name:            expand_imm64_sext_shrink_to_bfrev
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    $vgpr0_vgpr1 = V_MOV_B64_PSEUDO -9223372036854775808, implicit $exec
+...
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -1729,10 +1729,10 @@
           .addImm(0); // clamp
       } else {
         BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
-          .addImm(Lo.getZExtValue())
+          .addImm(Lo.getSExtValue())
           .addReg(Dst, RegState::Implicit | RegState::Define);
         BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
-          .addImm(Hi.getZExtValue())
+          .addImm(Hi.getSExtValue())
           .addReg(Dst, RegState::Implicit | RegState::Define);
       }
     } else {


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