[PATCH] D105390: [X86] Lower insertions into non-0'th 128-bit subvector as broadcast+blend (PR50971)

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


================
Comment at: llvm/test/CodeGen/X86/insertelement-shuffle.ll:44
+; X64_AVX256-NEXT:    vmovq %xmm2, %rax
+; X64_AVX256-NEXT:    vmovq %rax, %xmm2
+; X64_AVX256-NEXT:    vpbroadcastq %xmm2, %ymm2
----------------
RKSimon wrote:
> Any idea whats going on here?
```
Optimized legalized selection DAG: %bb.0 'insert_subvector_512:'
SelectionDAG has 24 nodes:
  t0: ch = EntryToken
      t6: v4i64,ch = CopyFromReg t0, Register:v4i64 %2
                t2: i32,ch = CopyFromReg t0, Register:i32 %0
              t41: v4i32 = scalar_to_vector t2
              t4: i32,ch = CopyFromReg t0, Register:i32 %1
            t43: v4i32 = insert_vector_elt t41, t4, Constant:i64<1>
          t35: v2i64 = bitcast t43
        t36: i64 = extract_vector_elt t35, Constant:i64<0>
      t47: v4i64 = X86ISD::VBROADCAST t36
    t45: v4i64 = X86ISD::BLENDI t6, t47, TargetConstant:i8<4>
  t26: ch,glue = CopyToReg t0, Register:v4i64 $ymm0, t45
    t8: v4i64,ch = CopyFromReg t0, Register:v4i64 %3
  t28: ch,glue = CopyToReg t26, Register:v4i64 $ymm1, t8, t26:1
  t29: ch = X86ISD::RET_FLAG t28, TargetConstant:i32<0>, Register:v4i64 $ymm0, Register:v4i64 $ymm1, t28:1
```
We were missing `broadcast(extract_vector_elt(x, 0)) -> broadcast(x)` fold.


Repository:
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  https://reviews.llvm.org/D105390/new/

https://reviews.llvm.org/D105390